From patchwork Fri Feb 20 18:01:09 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Coquelin X-Patchwork-Id: 442088 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 1F24B140161 for ; Sat, 21 Feb 2015 05:05:44 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754972AbbBTSCE (ORCPT ); Fri, 20 Feb 2015 13:02:04 -0500 Received: from mail-wi0-f194.google.com ([209.85.212.194]:51335 "EHLO mail-wi0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754938AbbBTSCA (ORCPT ); Fri, 20 Feb 2015 13:02:00 -0500 Received: by mail-wi0-f194.google.com with SMTP id hi2so1794544wib.1; Fri, 20 Feb 2015 10:01:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:in-reply-to:references; bh=/T64dNNqo9+Co+bJALxPRrLJHWpAySFUKgBluQWiguo=; b=asQdcQS7PkX/TqeEGBFZI0wWE+YrQpHqk39TQ+q0nvFBqWzcGaoR4bb42sJNVGHPjj DZHQ4kys8VuO5YPUaXlmZDy65P/Ncacbeppju8Vl+JLjdtd4LDniyC2dpfX4J0cRN2l4 RGvtpWCpyY6JhUOlaFEoPWSY6VH48td03R5Aku+Rpurmo5vCPVFKHw7qyWg4GLeH0wA+ c4e1AzFjiho0FDe0+2Vr5nWGu+muOg02+s1ravyPYHD+aFEKDN1+M8GbGWSl+4Gm9QoL p03yAZZPf3ZEcKKxQvQpgsycmthoGRe4thjGbxjBe08eIbGgI3RUpWkcwgKXOtbNvKNA 3jYA== X-Received: by 10.180.8.65 with SMTP id p1mr139374wia.42.1424455318593; Fri, 20 Feb 2015 10:01:58 -0800 (PST) Received: from lmecul0520.st.com. (169.20.90.92.rev.sfr.net. [92.90.20.169]) by mx.google.com with ESMTPSA id hs7sm3398370wib.4.2015.02.20.10.01.54 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 20 Feb 2015 10:01:58 -0800 (PST) From: Maxime Coquelin To: u.kleine-koenig@pengutronix.de, afaerber@suse.de, geert@linux-m68k.org, Rob Herring , Philipp Zabel , Jonathan Corbet , Maxime Coquelin , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , Daniel Lezcano , Thomas Gleixner , Linus Walleij , Greg Kroah-Hartman , Jiri Slaby , Arnd Bergmann , Andrew Morton , "David S. Miller" , Mauro Carvalho Chehab , Joe Perches , Antti Palosaari , Tejun Heo , Will Deacon , Nikolay Borisov , Rusty Russell , Kees Cook , Michal Marek , linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org Subject: [PATCH v2 10/18] dt-bindings: Document the STM32 pin controller Date: Fri, 20 Feb 2015 19:01:09 +0100 Message-Id: <1424455277-29983-11-git-send-email-mcoquelin.stm32@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1424455277-29983-1-git-send-email-mcoquelin.stm32@gmail.com> References: <1424455277-29983-1-git-send-email-mcoquelin.stm32@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This adds documentation of device tree bindings for the STM32 pin controller. Signed-off-by: Maxime Coquelin --- .../devicetree/bindings/pinctrl/pinctrl-stm32.txt | 99 ++++++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-stm32.txt diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-stm32.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-stm32.txt new file mode 100644 index 0000000..0fb5b24 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-stm32.txt @@ -0,0 +1,99 @@ +* STM32 GPIO and Pin Mux/Config controller + +STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware +controller. It controls the input/output settings on the available pins and +also provides ability to multiplex and configure the output of various on-chip +controllers onto these pads. + +Pin controller node: +Required properies: +- compatible : "st,stm32-pinctrl" +- #address-cells: The value of this property must be 1 +- #size-cells : The value of this property must be 1 +- ranges : defines mapping between pin controller node (parent) to + gpio-bank node (children). + +GPIO controller/bank node: +Required properties: +- gpio-controller : Indicates this device is a GPIO controller +- #gpio-cells : Should be two. + The first cell is the pin number + The second one is the polarity: + - 0 for active high + - 1 for active low +- reg : The gpio address range, relative to the pinctrl range +- st,bank-name : Should be a name string for this bank as specified in + the datasheet + +Optional properties: +- reset: : Reference to the reset controller + +Example: +#include +... + + pin-controller { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32-pinctrl"; + ranges = <0 0x40020000 0x3000>; + + gpioa: gpio@40020000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + resets = <&reset_ahb1 0>; + st,bank-name = "GPIOA"; + }; + ... + pin-functions nodes follow... + }; + +Contents of function subnode node: +---------------------------------- + +Required properties for pin configuration node: +- st,pins : Child node with list of pins with configuration. + +Below is the format of how each pin conf should look like. + + + +Every PIO is represented with 4 to 6 parameters. +Each parameter is explained as below. + +- bank : Should be bank phandle to which this PIO belongs. +- offset : Offset in the PIO bank. +- altmode : Should be mode or alternate function number associated this pin, as +described in the datasheet (IN, OUT, ALT0...ALT15, ANALOG) +- pull : Should be either NO_PULL, PULL_UP or PULL_DOWN +- type : Should be either PUSH_PULL or OPEN_DRAIN. + Setting it is not needed for IN and ANALOG modes, or alternate + functions acting as inputs. +- speed : Value taken from the datasheet, depending on the function +(LOW_SPEED, MEDIUM_SPEED, FAST_SPEED, HIGH_SPEED) + Setting it is not needed for IN and ANALOG modes, or alternate + functions acting as inputs. + +usart1 { + pinctrl_usart1: usart1-0 { + st,pins { + tx = <&gpioa 9 ALT7 NO_PULL PUSH_PULL LOW_SPEED>; + rx = <&gpioa 10 ALT7 NO_PULL PUSH_PULL LOW_SPEED>; + }; + }; +}; + +adc2 { + pinctrl_adc2: adc2-0 { + st,pins { + adc0 = <&gpioe 4 ANALOG NO_PULL>; + }; + }; +}; + +usart1: usart@40011000 { + ... + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; +};