From patchwork Mon Dec 8 15:07:53 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Ribalda Delgado X-Patchwork-Id: 418719 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 5AB23140082 for ; Tue, 9 Dec 2014 02:09:39 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755642AbaLHPJi (ORCPT ); Mon, 8 Dec 2014 10:09:38 -0500 Received: from mail-la0-f49.google.com ([209.85.215.49]:53534 "EHLO mail-la0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755480AbaLHPIC (ORCPT ); Mon, 8 Dec 2014 10:08:02 -0500 Received: by mail-la0-f49.google.com with SMTP id hs14so3961362lab.8 for ; Mon, 08 Dec 2014 07:08:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=K5yY8W3tQROYpg4JQx6nG7pZ8OSePRkVhbGsgXPlz4Y=; b=KO/Kahuref7exa/1i55jlAnFyhZ5XL6jhmH61Z+QTk43SR9B2cFGNjBsNXeg7tjAzM K65EcgEatNlHkcSZ2zJ0+8c3Cw9gTxjQQeNfwaF6NjFFwcIwA9XMl8tiMHWOVfKWZ3RF sAZCslSqfa3Xjc6JGEbtvilAUEvIYA0ew9YaB5ChaLhcCj8LJqPhWxLpBxojQAXt02fe TgFjMPXQDV3yR4lwEnnEp+cGMsNP9MwJQ7gedcHGGgzlSEVsYW0oCeCB/CjeXh/F/k8R 4VA7++Vi4WEBITdDE80L9/ET9U45E/mPoSYMX9630q6PVp8+MtvNX6GiGFbYVeivGLmF m7UA== X-Received: by 10.152.27.41 with SMTP id q9mr17033499lag.69.1418051280745; Mon, 08 Dec 2014 07:08:00 -0800 (PST) Received: from neopili.qtec.com (cpe.xe-3-0-1-778.vbrnqe10.dk.customer.tdc.net. [80.197.57.18]) by mx.google.com with ESMTPSA id w3sm10765909law.36.2014.12.08.07.07.59 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 Dec 2014 07:08:00 -0800 (PST) From: Ricardo Ribalda Delgado To: Linus Walleij , Alexandre Courbot , Michal Simek , =?UTF-8?q?S=C3=B6ren=20Brinkmann?= , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ricardo Ribalda Delgado Subject: [PATCH 1/4] gpio/xilinx: remove offset property Date: Mon, 8 Dec 2014 16:07:53 +0100 Message-Id: <1418051276-5476-2-git-send-email-ricardo.ribalda@gmail.com> X-Mailer: git-send-email 2.1.3 In-Reply-To: <1418051276-5476-1-git-send-email-ricardo.ribalda@gmail.com> References: <1418051276-5476-1-git-send-email-ricardo.ribalda@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Instead of calculating the register offset per call, pre-calculate it on probe time. Signed-off-by: Ricardo Ribalda Delgado Acked-by: Alexandre Courbot --- drivers/gpio/gpio-xilinx.c | 33 +++++++++++---------------------- 1 file changed, 11 insertions(+), 22 deletions(-) diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c index ba18b06..9483950 100644 --- a/drivers/gpio/gpio-xilinx.c +++ b/drivers/gpio/gpio-xilinx.c @@ -50,7 +50,6 @@ struct xgpio_instance { struct of_mm_gpio_chip mmchip; u32 gpio_state; u32 gpio_dir; - u32 offset; spinlock_t gpio_lock; }; @@ -65,12 +64,8 @@ struct xgpio_instance { static int xgpio_get(struct gpio_chip *gc, unsigned int gpio) { struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); - struct xgpio_instance *chip = - container_of(mm_gc, struct xgpio_instance, mmchip); - void __iomem *regs = mm_gc->regs + chip->offset; - - return !!(xgpio_readreg(regs + XGPIO_DATA_OFFSET) & BIT(gpio)); + return !!(xgpio_readreg(mm_gc->regs + XGPIO_DATA_OFFSET) & BIT(gpio)); } /** @@ -88,7 +83,6 @@ static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); struct xgpio_instance *chip = container_of(mm_gc, struct xgpio_instance, mmchip); - void __iomem *regs = mm_gc->regs; spin_lock_irqsave(&chip->gpio_lock, flags); @@ -98,8 +92,7 @@ static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) else chip->gpio_state &= ~BIT(gpio); - xgpio_writereg(regs + chip->offset + XGPIO_DATA_OFFSET, - chip->gpio_state); + xgpio_writereg(mm_gc->regs + XGPIO_DATA_OFFSET, chip->gpio_state); spin_unlock_irqrestore(&chip->gpio_lock, flags); } @@ -119,13 +112,12 @@ static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); struct xgpio_instance *chip = container_of(mm_gc, struct xgpio_instance, mmchip); - void __iomem *regs = mm_gc->regs; spin_lock_irqsave(&chip->gpio_lock, flags); /* Set the GPIO bit in shadow register and set direction as input */ chip->gpio_dir |= BIT(gpio); - xgpio_writereg(regs + chip->offset + XGPIO_TRI_OFFSET, chip->gpio_dir); + xgpio_writereg(mm_gc->regs + XGPIO_TRI_OFFSET, chip->gpio_dir); spin_unlock_irqrestore(&chip->gpio_lock, flags); @@ -148,7 +140,6 @@ static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); struct xgpio_instance *chip = container_of(mm_gc, struct xgpio_instance, mmchip); - void __iomem *regs = mm_gc->regs; spin_lock_irqsave(&chip->gpio_lock, flags); @@ -157,12 +148,11 @@ static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) chip->gpio_state |= BIT(gpio); else chip->gpio_state &= ~BIT(gpio); - xgpio_writereg(regs + chip->offset + XGPIO_DATA_OFFSET, - chip->gpio_state); + xgpio_writereg(mm_gc->regs + XGPIO_DATA_OFFSET, chip->gpio_state); /* Clear the GPIO bit in shadow register and set direction as output */ chip->gpio_dir &= ~BIT(gpio); - xgpio_writereg(regs + chip->offset + XGPIO_TRI_OFFSET, chip->gpio_dir); + xgpio_writereg(mm_gc->regs + XGPIO_TRI_OFFSET, chip->gpio_dir); spin_unlock_irqrestore(&chip->gpio_lock, flags); @@ -178,10 +168,8 @@ static void xgpio_save_regs(struct of_mm_gpio_chip *mm_gc) struct xgpio_instance *chip = container_of(mm_gc, struct xgpio_instance, mmchip); - xgpio_writereg(mm_gc->regs + chip->offset + XGPIO_DATA_OFFSET, - chip->gpio_state); - xgpio_writereg(mm_gc->regs + chip->offset + XGPIO_TRI_OFFSET, - chip->gpio_dir); + xgpio_writereg(mm_gc->regs + XGPIO_DATA_OFFSET, chip->gpio_state); + xgpio_writereg(mm_gc->regs + XGPIO_TRI_OFFSET, chip->gpio_dir); } /** @@ -247,9 +235,6 @@ static int xgpio_of_probe(struct device_node *np) if (!chip) return -ENOMEM; - /* Add dual channel offset */ - chip->offset = XGPIO_CHANNEL_OFFSET; - /* Update GPIO state shadow register with default value */ of_property_read_u32(np, "xlnx,dout-default-2", &chip->gpio_state); @@ -285,6 +270,10 @@ static int xgpio_of_probe(struct device_node *np) np->full_name, status); return status; } + + /* Add dual channel offset */ + chip->mmchip.regs += XGPIO_CHANNEL_OFFSET; + pr_info("XGpio: %s: dual channel registered, base is %d\n", np->full_name, chip->mmchip.gc.base); }