From patchwork Tue Nov 18 23:49:55 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 412222 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 0E217140142 for ; Wed, 19 Nov 2014 10:51:12 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932940AbaKRXuP (ORCPT ); Tue, 18 Nov 2014 18:50:15 -0500 Received: from mail-ie0-f171.google.com ([209.85.223.171]:59555 "EHLO mail-ie0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932938AbaKRXuL (ORCPT ); Tue, 18 Nov 2014 18:50:11 -0500 Received: by mail-ie0-f171.google.com with SMTP id rl12so4733041iec.30 for ; Tue, 18 Nov 2014 15:50:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Mq/q57BsZeHt60mw2cj8m3GEVvqC7s0l4ws6GniyqM8=; b=gqj3f6O1hsWVJWL696RmOjNFVYEihQ+xK/hGVqLfYAS4KR+MrqwMkQ9zTr48/Bw1mc ch5Bkep0zWtDlIel4DAQXnh9mhSnI8bB9bacjlS4maOx+IM2LzvrY69KLwSkuNgbHLXI 8whR4jZ+C3J7z9ND/UgmjYONA7xguG3UCILLo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Mq/q57BsZeHt60mw2cj8m3GEVvqC7s0l4ws6GniyqM8=; b=KnLDOpcpF40UsMQIwjKPwcyC/f1EyvK1MeEPT8nVYfGKjewL2vPdIPel2deI0Nh2LS 2C6Wj1RXYsc7sS46cFWFY6Gzw4YBPRCGIyFWrvZxVsVdA837zx7NsfaHrAQMBm4P8Vpo P0Yx/Z+zrBzCzDW5OIQVik0OjA93JFhbsaMMqlaOUUkQPq9d8cXQHDJk7fwna7kh8YX4 dnHpXAoov5Jvl+Oa7jTzvJ4p8fiw/fKulEZKGokWawdrJ6pNrnwZ1awOMcoJDfJuqXIx 48xu0o484c/ZH5MC+QJxFQBx0tifvhV+4aVxJPxgsQXNO5/Os0crA1YMH2C1i7IKBSTB oFnQ== X-Gm-Message-State: ALoCoQn/Kexz1ftt1+yD58MfNeBNikypc0oIBghGOwgmFvB6tajxZF0ywANkQHRrlZrITKOyep84 X-Received: by 10.50.39.80 with SMTP id n16mr6921935igk.49.1416354610163; Tue, 18 Nov 2014 15:50:10 -0800 (PST) Received: from tictac.mtv.corp.google.com ([172.22.65.76]) by mx.google.com with ESMTPSA id c62sm7592185ioe.22.2014.11.18.15.50.09 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Nov 2014 15:50:09 -0800 (PST) From: Doug Anderson To: Heiko Stuebner , Linus Walleij Cc: Sonny Rao , Dmitry Torokhov , Chris Zhong , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Doug Anderson , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] pinctrl: rockchip: Handle wakeup pins Date: Tue, 18 Nov 2014 15:49:55 -0800 Message-Id: <1416354596-15013-2-git-send-email-dianders@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 In-Reply-To: <1416354596-15013-1-git-send-email-dianders@chromium.org> References: <1416354596-15013-1-git-send-email-dianders@chromium.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The rockchip pinctrl driver was using irq_gc_set_wake() as its implementation of irq_set_wake() but was totally ignoring everything that irq_gc_set_wake() did (which is to upkeep gc->wake_active). Let's fix that by setting gc->wake_active as GPIO_INTEN at suspend time and restoring GPIO_INTEN at resume time. NOTE a few quirks when thinking about this patch: - Rockchip pinctrl hardware supports both "disable/enable" and "mask/unmask". Right now we only use "disable/enable" and present those to Linux as "mask/unmask". This should be OK because enable/disable is optional and Linux will implement it in terms of mask/unmask. At the moment we always tell hardware all interrupts are unmasked (the boot default). - At suspend time Linux tries to call "disable" on all interrupts and also enables wakeup on all wakeup interrupts. One would think that since "disable" is implemented as "mask" when "disable" isn't provided and that since we were ignoring gc->wake_active that nothing would have woken us up. That's not the case since Linux "optimizes" things and just leaves interrutps unmasked, assuming it could mask them later when they go off. That meant that at suspend time all interrupts were actually being left enabled. With this patch random non-wakeup interrupts no longer wake the system up. Wakeup interrupts still wake the system up. Signed-off-by: Doug Anderson Reviewed-by: Dmitry Torokhov Reviewed-by: Heiko Stuebner --- drivers/pinctrl/pinctrl-rockchip.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index ba74f0a..e91e845 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -89,6 +89,7 @@ struct rockchip_iomux { * @reg_pull: optional separate register for additional pull settings * @clk: clock of the gpio bank * @irq: interrupt of the gpio bank + * @saved_enables: Saved content of GPIO_INTEN at suspend time. * @pin_base: first pin number * @nr_pins: number of pins in this bank * @name: name of the bank @@ -107,6 +108,7 @@ struct rockchip_pin_bank { struct regmap *regmap_pull; struct clk *clk; int irq; + u32 saved_enables; u32 pin_base; u8 nr_pins; char *name; @@ -1543,6 +1545,23 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) return 0; } +static void rockchip_irq_suspend(struct irq_data *d) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct rockchip_pin_bank *bank = gc->private; + + bank->saved_enables = irq_reg_readl(gc, GPIO_INTEN); + irq_reg_writel(gc, gc->wake_active, GPIO_INTEN); +} + +static void rockchip_irq_resume(struct irq_data *d) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct rockchip_pin_bank *bank = gc->private; + + irq_reg_writel(gc, bank->saved_enables, GPIO_INTEN); +} + static int rockchip_interrupts_register(struct platform_device *pdev, struct rockchip_pinctrl *info) { @@ -1587,6 +1606,8 @@ static int rockchip_interrupts_register(struct platform_device *pdev, gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; + gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; + gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; gc->wake_enabled = IRQ_MSK(bank->nr_pins);