From patchwork Mon Sep 1 12:53:41 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anders Berg X-Patchwork-Id: 384818 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 650F31401AC for ; Mon, 1 Sep 2014 23:01:41 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753316AbaIANBk (ORCPT ); Mon, 1 Sep 2014 09:01:40 -0400 Received: from exprod7og105.obsmtp.com ([64.18.2.163]:48385 "EHLO exprod7og105.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753065AbaIANBk (ORCPT ); Mon, 1 Sep 2014 09:01:40 -0400 Received: from mail-qc0-f178.google.com ([209.85.216.178]) (using TLSv1) by exprod7ob105.postini.com ([64.18.6.12]) with SMTP ID DSNKVARuM45XKUE6H2omqW1Q0ev+a24UI+m4@postini.com; Mon, 01 Sep 2014 06:01:40 PDT Received: by mail-qc0-f178.google.com with SMTP id x13so5287594qcv.37 for ; Mon, 01 Sep 2014 06:01:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sldEDksAGYpGUXaiOd1xGPbQGMPK/VqoHyE6oTfFhhE=; b=k88PTevK79yNww9K2532V8eKE+l0pOYY8AjImtY5+Oa4Ey9txeHgiVjHkSZ9seE3Ul QQJy793C1eHaXRnaqk3GnxLPe8XOLegq0Iv//nTIchd7I70ygVWJk7L9Avx2skGeOK0x fWOh4VUHWpJAAPOApQTITpE+xztlE9IkuFhPRpMOksp0FvOqDONQLqAzfsRLgIq2nyMH Ft3V/dj+S/FCe7T+nm8v2jMuQrI3wlLSK0BxI6TIANWFKo9N+oq2C8S9t34wRTsRRrZS Fd13OvRt0PCs3uwkMbRrOHm341RTdkei016Ej0ZUQydGzKwqyrls2F/15xiLN4dfaBmW AWNw== X-Received: by 10.224.74.67 with SMTP id t3mr44747576qaj.100.1409576049610; Mon, 01 Sep 2014 05:54:09 -0700 (PDT) X-Gm-Message-State: ALoCoQl7Zgett3hm4dRQu8AYkzcdSFecERThnCqIi88kffDCIqcFYOZrtEendQFAXWs4jv34SLK5WiCP+6WB5FNP+BMv9diFD+db7K2VhU+uQgvlJGSbb6i3Dva3pj2dL6p2QQC0DeV3aLKgcJqpb+U8zvUpcMb3Zg== X-Received: by 10.224.74.67 with SMTP id t3mr44747558qaj.100.1409576049526; Mon, 01 Sep 2014 05:54:09 -0700 (PDT) Received: from swsaberg01.lsi.com ([213.121.150.226]) by mx.google.com with ESMTPSA id i17sm1813745qay.47.2014.09.01.05.54.07 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 01 Sep 2014 05:54:09 -0700 (PDT) From: Anders Berg To: Linus Walleij , Alexandre Courbot Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Anders Berg Subject: [PATCH 2/2] Documentation: DT bindings for AXM55xx SSP CS Date: Mon, 1 Sep 2014 14:53:41 +0200 Message-Id: <1409576021-24828-3-git-send-email-anders.berg@avagotech.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1409576021-24828-1-git-send-email-anders.berg@avagotech.com> References: <1409576021-24828-1-git-send-email-anders.berg@avagotech.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Bindings and documentation for AXM55xx SSP chip select controller. Signed-off-by: Anders Berg --- .../devicetree/bindings/gpio/gpio-axxia-sspcs.txt | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-axxia-sspcs.txt diff --git a/Documentation/devicetree/bindings/gpio/gpio-axxia-sspcs.txt b/Documentation/devicetree/bindings/gpio/gpio-axxia-sspcs.txt new file mode 100644 index 0000000..a64c695 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-axxia-sspcs.txt @@ -0,0 +1,36 @@ +* Axxia SSP GPIO chip-select driver + +The Axxia device has a ARM PL022 Prime Cell SSP controller with an extension of +five chip select signals that may be controlled by software. This driver +exports them as GPIOs. + +Required properties: + + * compatible: should be "lsi,ssp-gpio" + * reg: address of the chip select control register. + * gpio-controller: mark the device as gpio controller + * #gpio-cells: should be 1 and this field specifies the chip select number + +Example: +------- + + spics: sspgpio@2010088030 { + compatible = "lsi,ssp-gpio"; + #gpio-cells = <1>; + reg = <0x20 0x10088030 0x00 0x4>; + gpio-controller; + }; + + spi0: ssp@2010088000 { + compatible = "arm,pl022", "arm,primecell"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x20 0x10088000 0x00 0x1000>; + num-cs = <5>; + cs-gpios = <&spics 0>, + <&spics 1>, + <&spics 2>, + <&spics 3>, + <&spics 4>; + ... + };