mbox series

[v2,0/6] pinctrl: sunxi: Allwinner D1 support

Message ID 20220713025233.27248-1-samuel@sholland.org
Headers show
Series pinctrl: sunxi: Allwinner D1 support | expand

Message

Samuel Holland July 13, 2022, 2:52 a.m. UTC 
In the interest of keeping the series ready for v5.20, I decided to drop
the D1s bits so we can decide how to handle the compatibles next cycle.

This series adds pinctrl support for the Allwinner D1 SoC. First,
it updates the I/O bias code to support the new mode found on the D1
(as well as some existing SoCs). Then it refactors the driver to support
the new register layout found on the D1. Finally, it adds the new
driver.

The code size impact of the dynamic register layout ends up being just
over 100 bytes:

   text    data     bss     dec     hex filename
  11293     564       0   11857    2e51 pinctrl-sunxi.o (patch 3)
  11405     564       0   11969    2ec1 pinctrl-sunxi.o (patch 6)

This series was tested on A64, H6, and D1.

Changes in v2:
 - Drop D1s compatible for now, due to ongoing discussion
 - Fix PE3 function "csi0" -> "ncsi0"
 - Fix comments for JTAG DI/DO pins
 - Include channel numbers in PWM functions
 - Drop the separate D1s variant, since D1s is a non-conflicting subset
 - Enable the driver for MACH_SUN8I to cover T113 (same die, but ARMv7)

Samuel Holland (6):
  dt-bindings: pinctrl: Add compatible for Allwinner D1
  pinctrl: sunxi: Add I/O bias setting for H6 R-PIO
  pinctrl: sunxi: Support the 2.5V I/O bias mode
  pinctrl: sunxi: Refactor register/offset calculation
  pinctrl: sunxi: Make some layout parameters dynamic
  pinctrl: sunxi: Add driver for Allwinner D1

 .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml  |  13 +
 drivers/pinctrl/sunxi/Kconfig                 |   5 +
 drivers/pinctrl/sunxi/Makefile                |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c     | 840 ++++++++++++++++++
 drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c   |   2 +-
 drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c   |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c   |   2 +-
 drivers/pinctrl/sunxi/pinctrl-sunxi.c         | 156 +++-
 drivers/pinctrl/sunxi/pinctrl-sunxi.h         | 109 +--
 10 files changed, 999 insertions(+), 131 deletions(-)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c

Comments

Linus Walleij July 18, 2022, 9:40 a.m. UTC | #1 
On Wed, Jul 13, 2022 at 4:52 AM Samuel Holland <samuel@sholland.org> wrote:

> In the interest of keeping the series ready for v5.20, I decided to drop
> the D1s bits so we can decide how to handle the compatibles next cycle.
>
> This series adds pinctrl support for the Allwinner D1 SoC. First,
> it updates the I/O bias code to support the new mode found on the D1
> (as well as some existing SoCs). Then it refactors the driver to support
> the new register layout found on the D1. Finally, it adds the new
> driver.
>
> The code size impact of the dynamic register layout ends up being just
> over 100 bytes:
>
>    text    data     bss     dec     hex filename
>   11293     564       0   11857    2e51 pinctrl-sunxi.o (patch 3)
>   11405     564       0   11969    2ec1 pinctrl-sunxi.o (patch 6)
>
> This series was tested on A64, H6, and D1.
>
> Changes in v2:
>  - Drop D1s compatible for now, due to ongoing discussion
>  - Fix PE3 function "csi0" -> "ncsi0"
>  - Fix comments for JTAG DI/DO pins
>  - Include channel numbers in PWM functions
>  - Drop the separate D1s variant, since D1s is a non-conflicting subset
>  - Enable the driver for MACH_SUN8I to cover T113 (same die, but ARMv7)

Took out v1 and applied this v2 instead!

Thanks!
Linus Walleij