From patchwork Thu Dec 13 16:28:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 1012956 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=glider.be Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43Fzds0tJkz9s3Z for ; Fri, 14 Dec 2018 03:29:05 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729600AbeLMQ3E (ORCPT ); Thu, 13 Dec 2018 11:29:04 -0500 Received: from andre.telenet-ops.be ([195.130.132.53]:47924 "EHLO andre.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729473AbeLMQ3E (ORCPT ); Thu, 13 Dec 2018 11:29:04 -0500 Received: from ramsan ([84.194.111.163]) by andre.telenet-ops.be with bizsmtp id BUV21z00t3XaVaC01UV2lL; Thu, 13 Dec 2018 17:29:03 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan with esmtp (Exim 4.90_1) (envelope-from ) id 1gXTrC-0006KF-OK; Thu, 13 Dec 2018 17:29:02 +0100 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1gXTrC-0003ho-Lu; Thu, 13 Dec 2018 17:29:02 +0100 From: Geert Uytterhoeven To: Linus Walleij Cc: Laurent Pinchart , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 0/6] pinctrl: sh-pfc: Fix number of pins/marks mismatches Date: Thu, 13 Dec 2018 17:28:49 +0100 Message-Id: <20181213162855.14190-1-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hi all, This patch series fixes several mismatches between the number of pins and the number of marks in pin groups for Renesas SoCs. All of these have been detected by the last patch in the series, which adds a build-time check for this particular case. I believe none of the affected pins groups are configured by the DTS files supplied with the kernel. I intend to queue this up in sh-pfc-for-v4.21, as I will probably have other fixes to send a PR for anyway. Thanks for your comments! Geert Uytterhoeven (6): pinctrl: sh-pfc: r8a7740: Add missing REF125CK pin to gether_gmii group pinctrl: sh-pfc: r8a7740: Add missing LCD0 marks to lcd0_data24_1 group pinctrl: sh-pfc: r8a7791: Remove bogus ctrl marks from qspi_data4_b group pinctrl: sh-pfc: r8a7791: Remove bogus marks from vin1_b_data18 group pinctrl: sh-pfc: sh73a0: Add missing TO pin to tpu4_to3 group pinctrl: sh-pfc: Validate pins/marks in pin group at build time drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 3 ++- drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 6 +----- drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 1 + drivers/pinctrl/sh-pfc/sh_pfc.h | 3 ++- 4 files changed, 6 insertions(+), 7 deletions(-)