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Thu, 15 Feb 2024 22:08:02 +0000 (GMT) From: Eddie James To: linux-fsi@lists.ozlabs.org Subject: [PATCH 02/33] clk: ast2600: Add FSI parent clock with correct rate Date: Thu, 15 Feb 2024 16:07:28 -0600 Message-Id: <20240215220759.976998-3-eajames@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240215220759.976998-1-eajames@linux.ibm.com> References: <20240215220759.976998-1-eajames@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: qu9m3EEKVKG-DGbpYkJKjIZdu1nYUI1H X-Proofpoint-ORIG-GUID: qu9m3EEKVKG-DGbpYkJKjIZdu1nYUI1H X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-15_20,2024-02-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 priorityscore=1501 impostorscore=0 suspectscore=0 mlxlogscore=999 adultscore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 malwarescore=0 bulkscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402150171 X-BeenThere: linux-fsi@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robh@kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, sboyd@kernel.org, alistair@popple.id.au, mturquette@baylibre.com, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-clk@vger.kernel.org Errors-To: linux-fsi-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "linux-fsi" In order to calculate correct FSI bus clocks, the FSI clock must correctly calculate the rate from the parent (APLL / 4). Signed-off-by: Eddie James --- drivers/clk/clk-ast2600.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c index 909c3137c428..faf88324f7b1 100644 --- a/drivers/clk/clk-ast2600.c +++ b/drivers/clk/clk-ast2600.c @@ -19,7 +19,7 @@ * This includes the gates (configured from aspeed_g6_gates), plus the * explicitly-configured clocks (ASPEED_CLK_HPLL and up). */ -#define ASPEED_G6_NUM_CLKS 72 +#define ASPEED_G6_NUM_CLKS 73 #define ASPEED_G6_SILICON_REV 0x014 #define CHIP_REVISION_ID GENMASK(23, 16) @@ -157,7 +157,7 @@ static const struct aspeed_gate_data aspeed_g6_gates[] = { [ASPEED_CLK_GATE_UART11CLK] = { 59, -1, "uart11clk-gate", "uartx", 0 }, /* UART11 */ [ASPEED_CLK_GATE_UART12CLK] = { 60, -1, "uart12clk-gate", "uartx", 0 }, /* UART12 */ [ASPEED_CLK_GATE_UART13CLK] = { 61, -1, "uart13clk-gate", "uartx", 0 }, /* UART13 */ - [ASPEED_CLK_GATE_FSICLK] = { 62, 59, "fsiclk-gate", NULL, 0 }, /* FSI */ + [ASPEED_CLK_GATE_FSICLK] = { 62, 59, "fsiclk-gate", "fsiclk", 0 }, /* FSI */ }; static const struct clk_div_table ast2600_eclk_div_table[] = { @@ -821,6 +821,9 @@ static void __init aspeed_g6_cc(struct regmap *map) hw = clk_hw_register_fixed_factor(NULL, "i3cclk", "apll", 0, 1, 8); aspeed_g6_clk_data->hws[ASPEED_CLK_I3C] = hw; + + hw = clk_hw_register_fixed_factor(NULL, "fsiclk", "apll", 0, 1, 4); + aspeed_g6_clk_data->hws[ASPEED_CLK_FSI] = hw; }; static void __init aspeed_g6_cc_init(struct device_node *np)