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ARM: dts: aspeed-g5: Add SCU phandle to GFX node

Message ID 20210603064536.165297-1-joel@jms.id.au
State New
Headers show
Series ARM: dts: aspeed-g5: Add SCU phandle to GFX node | expand

Commit Message

Joel Stanley June 3, 2021, 6:45 a.m. UTC
In v5.13 the DRM driver gained support for using a phandle to the SCU,
instead of matching on the scu compatible.

Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 arch/arm/boot/dts/aspeed-g5.dtsi | 1 +
 1 file changed, 1 insertion(+)
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Patch

diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index d733c1f161c1..329eaeef66fb 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -264,6 +264,7 @@  gfx: display@1e6e6000 {
 				reg-io-width = <4>;
 				clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
 				resets = <&syscon ASPEED_RESET_CRT1>;
+				syscon = <&syscon>;
 				status = "disabled";
 				interrupts = <0x19>;
 			};