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s= fm1; bh=yoh1CaMONAFLRi9+PfS7AYrUFtUqN1k3CcqjucPe+oE=; b=rXmEXnC+ dbOQTLIZWBov0WKudlp3a9cXmumZubDe18806lEMg9SfejtJ+WLcTGtjcqgkK27T vvA4jzTnNTg6HEw0vOuXKFPqt9A8hNijIxaUJFc+J2UH+42Vfpi2LbY0RkYdVX7W a2Gc/KDeWRa843Oyv7enQI0bygPIRIPs2uMVPSD6Xo1wFGhR2NQQay/VUeSdAIpR vxXFi/1Q/xUJG9nk9RcxxP6OHGUQ+UPIbIoCQeSOnO3vW4LOy86rvYxEX2Mcyasz MQv9CWjSHcijSIBuFwk24HQx4WrC7vZhvrIOO2aMbVTNjfj1Culo4evNqZcvZKza KKMDhK5UqKom9Q== X-ME-Sender: Received: from keelia.lan (220-253-53-78.dyn.iinet.net.au [220.253.53.78]) by mail.messagingengine.com (Postfix) with ESMTPA id 0ADBA2489B; Thu, 19 Oct 2017 23:38:51 -0400 (EDT) From: Andrew Jeffery To: linux-gpio@vger.kernel.org Subject: [RFC PATCH 5/5] gpio: aspeed: Add support for reset tolerance Date: Fri, 20 Oct 2017 14:07:27 +1030 Message-Id: <20171020033727.21557-6-andrew@aj.id.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171020033727.21557-1-andrew@aj.id.au> References: <20171020033727.21557-1-andrew@aj.id.au> X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, ryan_chen@aspeedtech.com, linux-aspeed@lists.ozlabs.org, corbet@lwn.net, patches@opensource.cirrus.com, linus.walleij@linaro.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, ldewangan@nvidia.com, ckeepax@opensource.wolfsonmicro.com, frowand.list@gmail.com, openbmc@lists.ozlabs.org Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" Use the new pinconf parameter for reset tolerance to expose the associated capability of the Aspeed GPIO controller. Signed-off-by: Andrew Jeffery --- drivers/gpio/gpio-aspeed.c | 39 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index bfc53995064a..0492cd917178 100644 --- a/drivers/gpio/gpio-aspeed.c +++ b/drivers/gpio/gpio-aspeed.c @@ -60,6 +60,7 @@ struct aspeed_gpio_bank { uint16_t val_regs; uint16_t irq_regs; uint16_t debounce_regs; + uint16_t tolerance_regs; const char names[4][3]; }; @@ -70,48 +71,56 @@ static const struct aspeed_gpio_bank aspeed_gpio_banks[] = { .val_regs = 0x0000, .irq_regs = 0x0008, .debounce_regs = 0x0040, + .tolerance_regs = 0x001c, .names = { "A", "B", "C", "D" }, }, { .val_regs = 0x0020, .irq_regs = 0x0028, .debounce_regs = 0x0048, + .tolerance_regs = 0x003c, .names = { "E", "F", "G", "H" }, }, { .val_regs = 0x0070, .irq_regs = 0x0098, .debounce_regs = 0x00b0, + .tolerance_regs = 0x00ac, .names = { "I", "J", "K", "L" }, }, { .val_regs = 0x0078, .irq_regs = 0x00e8, .debounce_regs = 0x0100, + .tolerance_regs = 0x00fc, .names = { "M", "N", "O", "P" }, }, { .val_regs = 0x0080, .irq_regs = 0x0118, .debounce_regs = 0x0130, + .tolerance_regs = 0x012c, .names = { "Q", "R", "S", "T" }, }, { .val_regs = 0x0088, .irq_regs = 0x0148, .debounce_regs = 0x0160, + .tolerance_regs = 0x015c, .names = { "U", "V", "W", "X" }, }, { .val_regs = 0x01E0, .irq_regs = 0x0178, .debounce_regs = 0x0190, + .tolerance_regs = 0x018c, .names = { "Y", "Z", "AA", "AB" }, }, { - .val_regs = 0x01E8, - .irq_regs = 0x01A8, + .val_regs = 0x01e8, + .irq_regs = 0x01a8, .debounce_regs = 0x01c0, + .tolerance_regs = 0x01bc, .names = { "AC", "", "", "" }, }, }; @@ -531,6 +540,30 @@ static int aspeed_gpio_setup_irqs(struct aspeed_gpio *gpio, return 0; } +static int aspeed_gpio_reset_tolerance(struct gpio_chip *chip, + unsigned int offset, bool enable) +{ + struct aspeed_gpio *gpio = gpiochip_get_data(chip); + const struct aspeed_gpio_bank *bank; + unsigned long flags; + u32 val; + + bank = to_bank(offset); + + spin_lock_irqsave(&gpio->lock, flags); + val = readl(gpio->base + bank->tolerance_regs); + + if (enable) + val |= GPIO_BIT(offset); + else + val &= ~GPIO_BIT(offset); + + writel(val, gpio->base + bank->tolerance_regs); + spin_unlock_irqrestore(&gpio->lock, flags); + + return 0; +} + static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset) { if (!have_gpio(gpiochip_get_data(chip), offset)) @@ -768,6 +801,8 @@ static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset, param == PIN_CONFIG_DRIVE_OPEN_SOURCE) /* Return -ENOTSUPP to trigger emulation, as per datasheet */ return -ENOTSUPP; + else if (param == PIN_CONFIG_RESET_TOLERANT) + return aspeed_gpio_reset_tolerance(chip, offset, arg); return -ENOTSUPP; }