| Message ID | 20190614144431.21760-2-hch@lst.de |
|---|---|
| State | New |
| Headers | show |
| Series | [1/7] arm-nommu: remove the partial DMA_ATTR_NON_CONSISTENT support | expand |
On 6/14/19 3:44 PM, Christoph Hellwig wrote: > The arm-nommu DMA code supports DMA_ATTR_NON_CONSISTENT allocations, but > does not provide a cache_sync operation. This means any user of it > will never be able to actually transfer cache ownership and thus cause > coherency bugs. By the way, Documentation/DMA-attributes.txt doesn't specify cache_sync() as requirement for DMA_ATTR_NON_CONSISTENT it only states that it is responsibility of the driver to have all the correct and necessary sync points. > > Signed-off-by: Christoph Hellwig <hch@lst.de> > --- > arch/arm/mm/dma-mapping-nommu.c | 24 +++--------------------- > 1 file changed, 3 insertions(+), 21 deletions(-) > > diff --git a/arch/arm/mm/dma-mapping-nommu.c b/arch/arm/mm/dma-mapping-nommu.c > index f304b10e23a4..bc003df45546 100644 > --- a/arch/arm/mm/dma-mapping-nommu.c > +++ b/arch/arm/mm/dma-mapping-nommu.c > @@ -39,18 +39,7 @@ static void *arm_nommu_dma_alloc(struct device *dev, size_t size, > unsigned long attrs) > > { > - void *ret; > - > - /* > - * Try generic allocator first if we are advertised that > - * consistency is not required. > - */ > - > - if (attrs & DMA_ATTR_NON_CONSISTENT) > - return dma_direct_alloc_pages(dev, size, dma_handle, gfp, > - attrs); > - > - ret = dma_alloc_from_global_coherent(size, dma_handle); > + void *ret = dma_alloc_from_global_coherent(size, dma_handle); > > /* > * dma_alloc_from_global_coherent() may fail because: > @@ -70,16 +59,9 @@ static void arm_nommu_dma_free(struct device *dev, size_t size, > void *cpu_addr, dma_addr_t dma_addr, > unsigned long attrs) > { > - if (attrs & DMA_ATTR_NON_CONSISTENT) { > - dma_direct_free_pages(dev, size, cpu_addr, dma_addr, attrs); > - } else { > - int ret = dma_release_from_global_coherent(get_order(size), > - cpu_addr); > - > - WARN_ON_ONCE(ret == 0); > - } > + int ret = dma_release_from_global_coherent(get_order(size), cpu_addr); > > - return; > + WARN_ON_ONCE(ret == 0); > } > > static int arm_nommu_dma_mmap(struct device *dev, struct vm_area_struct *vma, > FWIW: Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com> Cheers Vladimir
On Mon, Jun 24, 2019 at 03:23:08PM +0100, Vladimir Murzin wrote: > On 6/14/19 3:44 PM, Christoph Hellwig wrote: > > The arm-nommu DMA code supports DMA_ATTR_NON_CONSISTENT allocations, but > > does not provide a cache_sync operation. This means any user of it > > will never be able to actually transfer cache ownership and thus cause > > coherency bugs. > > By the way, Documentation/DMA-attributes.txt doesn't specify cache_sync() as > requirement for DMA_ATTR_NON_CONSISTENT it only states that it is responsibility > of the driver to have all the correct and necessary sync points. True. dma_cache_sync has always been a rather odd interface, as it doesn't specify in what direction we need to sync and doesn't participate in our ownership protocol. So my mid-term plan is to kill it off and replace it with the existing dma_sync_* helpers. This series is the first step towards that.
diff --git a/arch/arm/mm/dma-mapping-nommu.c b/arch/arm/mm/dma-mapping-nommu.c index f304b10e23a4..bc003df45546 100644 --- a/arch/arm/mm/dma-mapping-nommu.c +++ b/arch/arm/mm/dma-mapping-nommu.c @@ -39,18 +39,7 @@ static void *arm_nommu_dma_alloc(struct device *dev, size_t size, unsigned long attrs) { - void *ret; - - /* - * Try generic allocator first if we are advertised that - * consistency is not required. - */ - - if (attrs & DMA_ATTR_NON_CONSISTENT) - return dma_direct_alloc_pages(dev, size, dma_handle, gfp, - attrs); - - ret = dma_alloc_from_global_coherent(size, dma_handle); + void *ret = dma_alloc_from_global_coherent(size, dma_handle); /* * dma_alloc_from_global_coherent() may fail because: @@ -70,16 +59,9 @@ static void arm_nommu_dma_free(struct device *dev, size_t size, void *cpu_addr, dma_addr_t dma_addr, unsigned long attrs) { - if (attrs & DMA_ATTR_NON_CONSISTENT) { - dma_direct_free_pages(dev, size, cpu_addr, dma_addr, attrs); - } else { - int ret = dma_release_from_global_coherent(get_order(size), - cpu_addr); - - WARN_ON_ONCE(ret == 0); - } + int ret = dma_release_from_global_coherent(get_order(size), cpu_addr); - return; + WARN_ON_ONCE(ret == 0); } static int arm_nommu_dma_mmap(struct device *dev, struct vm_area_struct *vma,
The arm-nommu DMA code supports DMA_ATTR_NON_CONSISTENT allocations, but does not provide a cache_sync operation. This means any user of it will never be able to actually transfer cache ownership and thus cause coherency bugs. Signed-off-by: Christoph Hellwig <hch@lst.de> --- arch/arm/mm/dma-mapping-nommu.c | 24 +++--------------------- 1 file changed, 3 insertions(+), 21 deletions(-)