From patchwork Tue Feb 23 23:24:55 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Buchbinder X-Patchwork-Id: 587127 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2001:1868:205::9]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 72F1A140322 for ; Wed, 24 Feb 2016 10:25:30 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=ZfXLdXht; dkim-atps=neutral Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aYMKe-00017T-Ho; Tue, 23 Feb 2016 23:25:28 +0000 Received: from mail-pf0-x22b.google.com ([2607:f8b0:400e:c00::22b]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aYMKc-0008Rb-F4 for linux-snps-arc@lists.infradead.org; Tue, 23 Feb 2016 23:25:27 +0000 Received: by mail-pf0-x22b.google.com with SMTP id x65so961092pfb.1 for ; Tue, 23 Feb 2016 15:25:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=Ezf+qwMECkvwjdFj809HvQzFyIbLjziRTCP50VhuT5o=; b=ZfXLdXhtjC+3insRtrzyZr3jljuC11kD8MtjDW5B7b3tHAG5oOYPDCC9qBLCc41NJK waJN0MbA01Ii7/iT5yDe9EwX7SRVCqXkl1q9lbOBsp+6vnRugEL3QiZeQ2iC65mxkozk CybWr4iTYt0JT1MCt3z81+fevGUPd9s45ejux3oYX9SpD0vyP3KWpx6q+xywsrgZApSv PkWWjwo/pGQI0hH78Y5WaXqeeHQ0zBSNV7vPjta9TEtsDVe3OEVlHV6GAAIdRYN+plF0 VMh4x2+iMaJlvxXIRoLCBz0FH+ALhdxTauKcP7iiZohgnN6VX4vCU5LkBNIBrXDwuLgQ Z6KQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Ezf+qwMECkvwjdFj809HvQzFyIbLjziRTCP50VhuT5o=; b=kyiCQ/3sioeAnAJSaIRI5wRFkOhlT/nE2ueJ1DzJR9rTAurCtKMu/t7fVp9qSJbWvQ CmBLOnTUdTc8kVO53G4TW+5ZLJ5vl+tOVNxMQaxCSRmoh+lImiIo/UFEx4rORM+8HLOZ bIamp0UjbANpuZw9caI5lQLLGbykSBvqOXN65Zv4cVhdji5FR9vlg5EQIHXVaj7TjKMR aj8BvIjebECMjBZuk44PKMkyeiL2hxcjDVK3+wm+BcveSuFWnn4FjLYEfwIB84zLFYno NneGRZZVAE1n350YQPoBe01qXgeeRLhoqdmhCoYiQfY1lytgdKOgKO8AI44UHJTJsTyC PWNA== X-Gm-Message-State: AG10YOTelzg8I6kwuAL7cRFhY5rX3DoIzh951rgykGNU6GjVe8ch/clIh3zAx5kaE3Szhg== X-Received: by 10.98.16.69 with SMTP id y66mr50131951pfi.86.1456269905530; Tue, 23 Feb 2016 15:25:05 -0800 (PST) Received: from abuchbinder-glaptop.corp.google.com ([172.19.65.109]) by smtp.gmail.com with ESMTPSA id v75sm109237pfa.39.2016.02.23.15.25.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 23 Feb 2016 15:25:04 -0800 (PST) From: Adam Buchbinder To: linux-snps-arc@lists.infradead.org Subject: [PATCH] ARC: Fix misspellings in comments. Date: Tue, 23 Feb 2016 15:24:55 -0800 Message-Id: <1456269895-25714-1-git-send-email-adam.buchbinder@gmail.com> X-Mailer: git-send-email 2.7.0.rc3.207.g0ac5344 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160223_152526_613956_AE5539B0 X-CRM114-Status: GOOD ( 13.97 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [2607:f8b0:400e:c00:0:0:0:22b listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (adam.buchbinder[at]gmail.com) -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-snps-arc@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: trivial@kernel.org, Adam Buchbinder MIME-Version: 1.0 Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Signed-off-by: Adam Buchbinder --- arch/arc/include/asm/cmpxchg.h | 2 +- arch/arc/include/asm/entry-compact.h | 2 +- arch/arc/include/asm/pgtable.h | 2 +- arch/arc/kernel/stacktrace.c | 2 +- arch/arc/kernel/time.c | 4 ++-- arch/arc/mm/cache.c | 2 +- arch/arc/mm/highmem.c | 2 +- arch/arc/mm/tlb.c | 8 ++++---- 8 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arc/include/asm/cmpxchg.h b/arch/arc/include/asm/cmpxchg.h index af7a2db..a444be6 100644 --- a/arch/arc/include/asm/cmpxchg.h +++ b/arch/arc/include/asm/cmpxchg.h @@ -149,7 +149,7 @@ static inline unsigned long __xchg(unsigned long val, volatile void *ptr, * Since xchg() doesn't always do that, it would seem that following defintion * is incorrect. But here's the rationale: * SMP : Even xchg() takes the atomic_ops_lock, so OK. - * LLSC: atomic_ops_lock are not relevent at all (even if SMP, since LLSC + * LLSC: atomic_ops_lock are not relevant at all (even if SMP, since LLSC * is natively "SMP safe", no serialization required). * UP : other atomics disable IRQ, so no way a difft ctxt atomic_xchg() * could clobber them. atomic_xchg() itself would be 1 insn, so it diff --git a/arch/arc/include/asm/entry-compact.h b/arch/arc/include/asm/entry-compact.h index 1aff3be..1d8f57c 100644 --- a/arch/arc/include/asm/entry-compact.h +++ b/arch/arc/include/asm/entry-compact.h @@ -231,7 +231,7 @@ /* free up r9 as scratchpad */ PROLOG_FREEUP_REG r9, @int\LVL\()_saved_reg - /* Which mode (user/kernel) was the system in when intr occured */ + /* Which mode (user/kernel) was the system in when intr occurred */ lr r9, [status32_l\LVL\()] SWITCH_TO_KERNEL_STK diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h index d426d42..ec2af62 100644 --- a/arch/arc/include/asm/pgtable.h +++ b/arch/arc/include/asm/pgtable.h @@ -12,7 +12,7 @@ * - Utilise some unused free bits to confine PTE flags to 12 bits * This is a must for 4k pg-sz * - * vineetg: Mar 2011 - changes to accomodate MMU TLB Page Descriptor mods + * vineetg: Mar 2011 - changes to accommodate MMU TLB Page Descriptor mods * -TLB Locking never really existed, except for initial specs * -SILENT_xxx not needed for our port * -Per my request, MMU V3 changes the layout of some of the bits diff --git a/arch/arc/kernel/stacktrace.c b/arch/arc/kernel/stacktrace.c index 001de4c..e0efff1 100644 --- a/arch/arc/kernel/stacktrace.c +++ b/arch/arc/kernel/stacktrace.c @@ -232,7 +232,7 @@ void show_stack(struct task_struct *tsk, unsigned long *sp) } /* Another API expected by schedular, shows up in "ps" as Wait Channel - * Ofcourse just returning schedule( ) would be pointless so unwind until + * Of course just returning schedule( ) would be pointless so unwind until * the function is not in schedular code */ unsigned int get_wchan(struct task_struct *tsk) diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c index 156d983..7d9a736 100644 --- a/arch/arc/kernel/time.c +++ b/arch/arc/kernel/time.c @@ -55,8 +55,8 @@ #define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */ #define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */ -#define TIMER_CTRL_IE (1 << 0) /* Interupt when Count reachs limit */ -#define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */ +#define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */ +#define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */ #define ARC_TIMER_MAX 0xFFFFFFFF diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c index b65f797..e1d71dc 100644 --- a/arch/arc/mm/cache.c +++ b/arch/arc/mm/cache.c @@ -650,7 +650,7 @@ static void __dma_cache_wback_l1(unsigned long start, unsigned long sz) /* * DMA ops for systems with both L1 and L2 caches, but without IOC - * Both L1 and L2 lines need to be explicity flushed/invalidated + * Both L1 and L2 lines need to be explicitly flushed/invalidated */ static void __dma_cache_wback_inv_slc(unsigned long start, unsigned long sz) { diff --git a/arch/arc/mm/highmem.c b/arch/arc/mm/highmem.c index 92dd92c..04f8332 100644 --- a/arch/arc/mm/highmem.c +++ b/arch/arc/mm/highmem.c @@ -18,7 +18,7 @@ /* * HIGHMEM API: * - * kmap() API provides sleep semantics hence refered to as "permanent maps" + * kmap() API provides sleep semantics hence referred to as "permanent maps" * It allows mapping LAST_PKMAP pages, using @last_pkmap_nr as the cursor * for book-keeping * diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c index daf2bf5..7046c12 100644 --- a/arch/arc/mm/tlb.c +++ b/arch/arc/mm/tlb.c @@ -45,7 +45,7 @@ * in interrupt-safe region. * * Vineetg: April 23rd Bug #93131 - * Problem: tlb_flush_kernel_range() doesnt do anything if the range to + * Problem: tlb_flush_kernel_range() doesn't do anything if the range to * flush is more than the size of TLB itself. * * Rahul Trivedi : Codito Technologies 2004 @@ -167,7 +167,7 @@ static void utlb_invalidate(void) /* MMU v2 introduced the uTLB Flush command. * There was however an obscure hardware bug, where uTLB flush would * fail when a prior probe for J-TLB (both totally unrelated) would - * return lkup err - because the entry didnt exist in MMU. + * return lkup err - because the entry didn't exist in MMU. * The Workround was to set Index reg with some valid value, prior to * flush. This was fixed in MMU v3 hence not needed any more */ @@ -210,7 +210,7 @@ static void tlb_entry_insert(unsigned int pd0, pte_t pd1) /* * Commit the Entry to MMU - * It doesnt sound safe to use the TLBWriteNI cmd here + * It doesn't sound safe to use the TLBWriteNI cmd here * which doesn't flush uTLBs. I'd rather be safe than sorry. */ write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite); @@ -636,7 +636,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned, * support. * * Normal and Super pages can co-exist (ofcourse not overlap) in TLB with a - * new bit "SZ" in TLB page desciptor to distinguish between them. + * new bit "SZ" in TLB page descriptor to distinguish between them. * Super Page size is configurable in hardware (4K to 16M), but fixed once * RTL builds. *