From patchwork Sun Dec 27 13:23:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Noam Camus X-Patchwork-Id: 561154 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2001:1868:205::9]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id B11B8140CC8 for ; Mon, 28 Dec 2015 00:27:58 +1100 (AEDT) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aDBMb-0000sA-8U; Sun, 27 Dec 2015 13:27:57 +0000 Received: from mail-am1on0082.outbound.protection.outlook.com ([157.56.112.82] helo=emea01-am1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aDBMY-0000qY-Cm for linux-snps-arc@lists.infradead.org; Sun, 27 Dec 2015 13:27:55 +0000 Received: from HE1PR02CA0065.eurprd02.prod.outlook.com (2a01:111:e400:5350::33) by AM3PR02MB1218.eurprd02.prod.outlook.com (2a01:111:e400:c407::12) with Microsoft SMTP Server (TLS) id 15.1.361.13; Sun, 27 Dec 2015 13:27:31 +0000 Received: from DB3FFO11FD038.protection.gbl (2a01:111:f400:7e04::176) by HE1PR02CA0065.outlook.office365.com (2a01:111:e400:5350::33) with Microsoft SMTP Server (TLS) id 15.1.361.13 via Frontend Transport; Sun, 27 Dec 2015 13:27:31 +0000 Authentication-Results: spf=fail (sender IP is 212.179.42.66) smtp.mailfrom=ezchip.com; kernel.org; dkim=none (message not signed) header.d=none; kernel.org; dmarc=none action=none header.from=ezchip.com; Received-SPF: Fail (protection.outlook.com: domain of ezchip.com does not designate 212.179.42.66 as permitted sender) receiver=protection.outlook.com; client-ip=212.179.42.66; helo=ezex10.ezchip.com; Received: from ezex10.ezchip.com (212.179.42.66) by DB3FFO11FD038.mail.protection.outlook.com (10.47.217.69) with Microsoft SMTP Server (TLS) id 15.1.355.15 via Frontend Transport; Sun, 27 Dec 2015 13:27:30 +0000 Received: from localhost.localdomain (10.1.3.132) by ezex10.ezchip.com (10.1.1.4) with Microsoft SMTP Server (TLS) id 14.3.224.2; Sun, 27 Dec 2015 15:27:07 +0200 From: Noam Camus To: Subject: [PATCH v5 04/20] clocksource: Add NPS400 timers driver Date: Sun, 27 Dec 2015 15:23:23 +0200 Message-ID: <1451222619-3610-5-git-send-email-noamc@ezchip.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1451222619-3610-1-git-send-email-noamc@ezchip.com> References: <1451222619-3610-1-git-send-email-noamc@ezchip.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-11.0.0.1191-8.000.1202-22026.007 X-TM-AS-Result: No--19.366600-8.000000-31 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1; DB3FFO11FD038; 1:JVf/iIpVgLo9NtNZLhG/WRTcB0zmw4JjHmacFwAuHNEC+9waWWEgyzC4YCbZ0crKBTHDfOA7APQVMn80rp/UPJwlYzoq3s48YfYnyIz1+6Taec9R221wki4GcsgYFqQRAPQvhc+nVH34S6Q+0vT+5BKWX0DyhcPcnU1fP5rpIdT5Ju/sipX/xUyyjbrc0lEnWk8/9f0XhPc6JNSsL2TpfUWm7CYjiDAArXNjlTXTwrpeuihVHy/EXUWeZ8IIJTwADvCc2WpnL0ckkhu88KGDVXIMFLV7jvPutzIQ6U5aExzcizvNqZdY6nKQ8/0gCLHpaRZqlkloUyOUE3+HzUTaQ0we3NKJQZaNajAXklVebNuD5CZJslM3af763bZnZq9HEcnp6fe3V3XgaMX8cS5Zj6ARcQ2CFgbb5NLnuTmKitY= X-Forefront-Antispam-Report: CIP:212.179.42.66; CTRY:IL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(2980300002)(1109001)(1110001)(339900001)(189002)(199003)(86362001)(11100500001)(575784001)(77096005)(33646002)(50466002)(2950100001)(229853001)(48376002)(87936001)(1096002)(5008740100001)(19580405001)(1220700001)(49486002)(2351001)(50986999)(5003940100001)(586003)(106466001)(5001970100001)(6806005)(85426001)(76176999)(105606002)(47776003)(50226001)(104016004)(92566002)(189998001)(36756003)(110136002)(19580395003)(2004002); DIR:OUT; SFP:1101; SCL:1; SRVR:AM3PR02MB1218; H:ezex10.ezchip.com; FPR:; SPF:Fail; PTR:ezmail.ezchip.com; MX:1; A:1; LANG:en; X-Microsoft-Exchange-Diagnostics: 1; AM3PR02MB1218; 2:osExzNVyq7+iM7WJGp7Jkxbz7ury4sZmxEoHtFVS50SSvHNzgk6PqYTSGd4WhRUYzD7QUhYie8lwCm93S7bp56oFcNe+VpUXnRIky8rPnyD1n5mh3NIGNIXXNAmmUe4ZpdW4IjJxLSqjjwRHSn93mw==; 3:QYpumwShSlq6qbw10yqCiXW8POtCozdmzcZ6zAZh0Q6HhehaLfGXSkAZUUMHhYoJVX7iyyIEwccwgy5RrccNCJe011t53i0A8nFGz3R6T2mkK/8Ob/4mDJ2jKKSenSTc8WLGUU9lkuT2HnFWQLJjIWHcAu5zi6un7tdr2/y2qDNu2B5TVx2Vi4WufYMDHtNk43sEDbyCNsgdayQhbgnOtT7pho+10RswskyR2nFgmRM=; 25:dweUQGc/cOmYS4FrXjJ71xLueH09WFGHIGLQuOEdhBuokGRGVNzQIG5vXvRb/iDBo7pvaJGIZ3ryEYgGplapHXbkWtSlug7II2q5/TPzct9glHTUj4uV6Xn2c+KyfetFRr5Gx4qF3ssxF6GCstldr+X85aNcIcVJC361pQWHyGWejCwCLrLMiTQLXhKg2YCYRtCmC13MHt/NHdO+YgAchSbbigzXj9QUGvOT3fT8se006c/Mjk9lVrT9VkxuakxX; 20:6WECgvS2jydVUJq1OYKTx4Dl8nXmGLOTCVfOZ13+x1gSk+z6yzO8ea62Wy42cbscjBAQe6NRqrlWOw6Tm5CKW12uhaj7c+Lo57tYCbjACjIy0NRsrU9paUraFb90Q0cE8wiMECCgD3wyDxE1JkB42ipuiuOXdvoE36A6Jyi4wUY= X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:AM3PR02MB1218; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(121898900299872); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(2401047)(5005006)(520078)(8121501046)(10201501046)(3002001); SRVR:AM3PR02MB1218; BCL:0; PCL:0; RULEID:; SRVR:AM3PR02MB1218; X-Microsoft-Exchange-Diagnostics: 1; AM3PR02MB1218; 4:G/41v9lZlHppEz54stx+ADZb0YAPpDSBhMu+9LP7eM83FGk8OvwM7bgr81jv4Wit4u63k6t3Fpuak2AK3/OJpWOnx0NDAtDcTI39uUW448cNnAJU1WtqThYiiZoQDwrKlOQFvoyvscjh9R+iCYkCBZvU4wuiw2w/PP3jTaiq7hvsuv3iFxo3+A8LQ+1RQeucMjTFjHa4MtaaXR686OMk2v6SlDGuFq0ZRR1/o0xCayqh6PvvtqMTZEh7vPXPpYsUdl77mc8vnpJOlNS8VLk0UfXMQB+GFTHkmg8ULQp0wEbCLQ9aPiRB9CbG6ub1mbnBVhvtYTxihQvdonodwUkUn0HS7qmQ/CJ171gTSitn1EFna8glg42UPE8TlCK4arpvmPrJDaNvJp2TzVYL9M59OOso8xq/9fXlrcqs3LQpyk4= X-Forefront-PRVS: 0803A0241F X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; AM3PR02MB1218; 23:RB9dOH9noTb+HsEqv0XAKumyJKJ8g10HvGKU4IP47?= =?us-ascii?Q?BosS20c+BhFMk7Z1zyL0DPUdqkrwqMyXICMSBfqcV67w6dFKYLw9HbL8KS+0?= =?us-ascii?Q?Io5G0FgqfmRgCJsixcsoTv72RCpcKrWsjD+lvvgD9mejVD3RcZ2uh1GGZVWK?= =?us-ascii?Q?QDizEfQZ1+PofLMtsg3NW9KGKf8KCX4v2V8M5bK++dzrR7K2xYGRWsfUZhVa?= =?us-ascii?Q?V9Y+ZBkfxCFEayEt2BWMPB4/pDVhQC/XFYT/LQCU36iEqeqV+6rJNkEAR261?= =?us-ascii?Q?jzqjmP8k01u/VWjAVVZum4CtRX7llgswP9hUqKgsQvYdis6GDs0KdP40IR+c?= =?us-ascii?Q?/qahFoLqyDO04sQcBgboG5lYnlafUxa/IQgjQf4jPRWVesEQloofJkvi9Mkx?= =?us-ascii?Q?E0SyXzObHL5yBsZr4w/ilGCuKPTIdf6c0lbH4wzTdFMl4FXs3zA3zImkwmUU?= =?us-ascii?Q?yG6j5ax7VNXAe5l91KRT6ijNbKTZeuDgq8xSR8ujtbwXupQSz3tknxVC+EWf?= =?us-ascii?Q?5Q2wioqbDg/sh4qP9TMvw5FwokofLKgb2vhwuaTRJKKGP75w1JOHJUV/GUW0?= =?us-ascii?Q?nHmx70qHtEUnLpvVXNipGDMNtrdpCwkl18IphvkmtEO9WrXGXdHeNBI5CMGR?= =?us-ascii?Q?Cb7JrClFPkGuuKFRIxHvoGVZeuZppjjCIjbZxbrnnfcCGQIHKpdfACZM19NP?= =?us-ascii?Q?MDXqaQWPfS2faQkQT6GTFUHtVXNNjvMQ0BI4d9T3sj1XoXWeoNfIRH/niimU?= =?us-ascii?Q?Xb8vVZVvoq70RSrvR/Lwx1WgjgNDbxEtUNtLLQJqpTwp7bwKCVBdQ0uzkN24?= =?us-ascii?Q?384JLvmKMmTkMJUX7adlHhUSsKETB1wYpsUK7y6/x90jfQ5b6sxLL+jQBRnz?= =?us-ascii?Q?m3A67eSFAoaUDfs2Losn0HUrBooaeC4gx/SmbCWS9z9dzGZgD2ndAEBudYaz?= =?us-ascii?Q?uSztMsP7NmXui6Sb4ckhhY9f/gJlBM1etUN2m4ve+1NoC8lMJGHk5X9rT0OG?= =?us-ascii?Q?1fEShornPruGTMMPGBjq5Rrs6vfWa0xDbyijNQDG/QUB+nbIsyMjD/iZXJTV?= =?us-ascii?Q?v7k77juFJtw8x9uOSFW7R/z1tEM?= X-Microsoft-Exchange-Diagnostics: 1; AM3PR02MB1218; 5:VIEy6Lk0LM/zMcZ28f537qmOTNKanx+77QNUO+ntHBi2FC9VA5IR1cM7cn0FNHwL8kLTsGHHD8ESl5PUXyhaKDvjEjxVwfhm5K4AF382O33/Di/t+ZQCzicZR2QvsZC8VLHACbcK7UnEwgi12Vgskg==; 24:dHxH5nayEosxjPKfIqN/W8aOUfQr2L518SM+BfFbBVcJCcqvgIHqV0ixI+OHQXKLbiZUYZQmMORbVamXMiS4CT+hjj06zIrsJTstEUC+UgU= SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: ezchip.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Dec 2015 13:27:30.3924 (UTC) X-MS-Exchange-CrossTenant-Id: 0fc16e0a-3cd3-4092-8b2f-0a42cff122c3 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0fc16e0a-3cd3-4092-8b2f-0a42cff122c3; Ip=[212.179.42.66]; Helo=[ezex10.ezchip.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR02MB1218 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151227_052754_910932_4B242DEC X-CRM114-Status: GOOD ( 20.09 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [157.56.112.82 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [157.56.112.82 listed in wl.mailspike.net] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-snps-arc@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marc.zyngier@arm.com, daniel.lezcano@linaro.org, linux-kernel@vger.kernel.org, cmetcalf@ezchip.com, Rob Herring , Noam Camus , John Stultz , Thomas Gleixner Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Noam Camus Add internal tick generator which is shared by all cores. Each cluster of cores view it through dedicated address. This is used for SMP system where all CPUs synced by same clock source. Signed-off-by: Noam Camus Cc: Daniel Lezcano Cc: Rob Herring Cc: Thomas Gleixner Cc: John Stultz Acked-by: Vineet Gupta --- .../bindings/timer/ezchip,nps400-timer.txt | 17 ++ drivers/clocksource/Kconfig | 7 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-nps.c | 199 ++++++++++++++++++++ 4 files changed, 224 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt create mode 100644 drivers/clocksource/timer-nps.c diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt new file mode 100644 index 0000000..eeb26d7 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt @@ -0,0 +1,17 @@ +NPS Network Processor + +Required properties: + +- compatible : should be "ezchip,nps400-timer" + +Clocks required for compatible = "ezchip,nps400-timer": +- clocks : Must contain a single entry describing the clock input +- interrupts : The interrupt of the first timer + +Example: + +timer { + compatible = "ezchip,nps400-timer"; + clocks = <&sysclk>; + interrupts = <3>; +}; diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 2eb5f0e..859e83d 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -132,6 +132,13 @@ config CLKSRC_TI_32K This option enables support for Texas Instruments 32.768 Hz clocksource available on many OMAP-like platforms. +config CLKSRC_NPS + bool "NPS400 clocksource driver" if COMPILE_TEST + select CLKSRC_OF if OF + help + NPS400 clocksource support. + Got 64 bit counter with update rate up to 1000MHz. + config CLKSRC_STM32 bool "Clocksource for STM32 SoCs" if !ARCH_STM32 depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST) diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 56bd16e..056cffd 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o obj-$(CONFIG_MTK_TIMER) += mtk_timer.o obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o +obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c new file mode 100644 index 0000000..b3fc9ba --- /dev/null +++ b/drivers/clocksource/timer-nps.c @@ -0,0 +1,199 @@ +/* + * Copyright(c) 2015 EZchip Technologies. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in + * the file called "COPYING". + */ + +#include +#include +#include +#include +#include +#include +#include + +#define NPS_MSU_TICK_LOW 0xC8 +#define NPS_CLUSTER_OFFSET 8 +#define NPS_CLUSTER_NUM 16 + +/* Timer related Aux registers */ +#define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */ +#define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */ +#define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */ + +#define TIMER_CTRL_IE (1 << 0) /* Interupt when Count reachs limit */ +#define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */ + +/* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */ +static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly; + +static unsigned long nps_timer_rate; +static int nps_timer_irq; + +static cycle_t nps_clksrc_read(struct clocksource *clksrc) +{ + int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET; + + return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]); +} + +static struct clocksource nps_counter = { + .name = "EZnps-tick", + .rating = 301, + .read = nps_clksrc_read, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static void nps_timer_event_setup(unsigned int cycles) +{ + write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles); + write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */ + + write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH); +} + +static int nps_clkevent_set_next_event(unsigned long delta, + struct clock_event_device *dev) +{ + nps_timer_event_setup(delta); + return 0; +} + +static int nps_clkevent_set_periodic(struct clock_event_device *dev) +{ + /* + * At X Hz, 1 sec = 1000ms -> X cycles; + * 10ms -> X / 100 cycles + */ + nps_timer_event_setup(nps_timer_rate / HZ); + return 0; +} + +static DEFINE_PER_CPU(struct clock_event_device, nps_clockevent_device) = { + .name = "nps_sys_timer", + .features = CLOCK_EVT_FEAT_ONESHOT | + CLOCK_EVT_FEAT_PERIODIC, + .rating = 300, + .set_next_event = nps_clkevent_set_next_event, + .set_state_periodic = nps_clkevent_set_periodic, +}; + +static int nps_timer_cpu_notify(struct notifier_block *self, + unsigned long action, void *hcpu) +{ + struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device); + + evt->irq = nps_timer_irq; + evt->cpumask = cpumask_of(smp_processor_id()); + + /* + * Grab cpu pointer in each case to avoid spurious + * preemptible warnings + */ + switch (action & ~CPU_TASKS_FROZEN) { + case CPU_STARTING: + enable_percpu_irq(nps_timer_irq, 0); + clockevents_config_and_register(evt, nps_timer_rate, + 0, ULONG_MAX); + break; + case CPU_DYING: + disable_percpu_irq(nps_timer_irq); + break; + } + + return NOTIFY_OK; +} + +static struct notifier_block nps_timer_cpu_nb = { + .notifier_call = nps_timer_cpu_notify, +}; + +static irqreturn_t nps_timer_irq_handler(int irq, void *dev_id) +{ + struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device); + int irq_reenable = clockevent_state_periodic(evt); + + /* + * Any write to CTRL reg ACks the interrupt, we rewrite the + * Count when [N]ot [H]alted bit. + * And re-arm it if perioid by [I]nterrupt [E]nable bit + */ + write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static void __init nps_setup_clocksource(struct device_node *node, + struct clk *clk, int irq) +{ + struct clocksource *clksrc = &nps_counter; + int ret, cluster; + + for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++) + nps_msu_reg_low_addr[cluster] = + nps_host_reg((cluster << NPS_CLUSTER_OFFSET), + NPS_MSU_BLKID, NPS_MSU_TICK_LOW); + + ret = clk_prepare_enable(clk); + if (ret) + pr_err("Couldn't enable parent clock\n"); + + nps_timer_rate = clk_get_rate(clk); + + ret = clocksource_register_hz(clksrc, nps_timer_rate); + if (ret) + pr_err("Couldn't register clock source.\n"); +} + +static void __init nps_setup_clockevents(struct device_node *node, + struct clk *clk, int irq) +{ + struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device); + int ret; + + register_cpu_notifier(&nps_timer_cpu_nb); + + evt->irq = irq; + evt->cpumask = cpumask_of(smp_processor_id()); + + clockevents_config_and_register(evt, nps_timer_rate, 0, ULONG_MAX); + + enable_percpu_irq(irq, 0); + + ret = request_percpu_irq(irq, nps_timer_irq_handler, + "timer", evt); + if (ret) + pr_err("Unable to register interrupt\n"); +} + +static void __init nps_timer_init(struct device_node *node) +{ + struct clk *clk; + + nps_timer_irq = irq_of_parse_and_map(node, 0); + if (nps_timer_irq <= 0) + panic("Can't parse IRQ"); + + clk = of_clk_get(node, 0); + if (IS_ERR(clk)) + panic("Can't get timer clock"); + + nps_setup_clocksource(node, clk, nps_timer_irq); + nps_setup_clockevents(node, clk, nps_timer_irq); +} + +CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer", + nps_timer_init);