| Message ID | 20210401150325.442125-32-npiggin@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | KVM: PPC: Book3S: C-ify the P9 entry/exit code | expand |
Hi Nicholas,
I love your patch! Yet something to improve:
[auto build test ERROR on powerpc/next]
[also build test ERROR on v5.12-rc5 next-20210401]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Nicholas-Piggin/KVM-PPC-Book3S-C-ify-the-P9-entry-exit-code/20210401-232743
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc64-randconfig-r033-20210402 (attached as .config)
compiler: powerpc64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/f2a35edda3ab6cba30fbfc362e163d5bc1e086d0
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Nicholas-Piggin/KVM-PPC-Book3S-C-ify-the-P9-entry-exit-code/20210401-232743
git checkout f2a35edda3ab6cba30fbfc362e163d5bc1e086d0
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=powerpc64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
arch/powerpc/kvm/book3s_hv_interrupt.c: In function 'switch_mmu_to_guest_radix':
arch/powerpc/kvm/book3s_hv_interrupt.c:61:46: error: 'struct kvm_vcpu_arch' has no member named 'nested'
61 | struct kvm_nested_guest *nested = vcpu->arch.nested;
| ^
arch/powerpc/kvm/book3s_hv_interrupt.c:80:2: error: implicit declaration of function 'kvmppc_check_need_tlb_flush' [-Werror=implicit-function-declaration]
80 | kvmppc_check_need_tlb_flush(kvm, vc->pcpu, nested);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from arch/powerpc/include/asm/processor.h:11,
from arch/powerpc/include/asm/thread_info.h:40,
from include/linux/thread_info.h:58,
from include/asm-generic/preempt.h:5,
from ./arch/powerpc/include/generated/asm/preempt.h:1,
from include/linux/preempt.h:78,
from include/linux/percpu.h:6,
from include/linux/context_tracking_state.h:5,
from include/linux/hardirq.h:5,
from include/linux/kvm_host.h:7,
from arch/powerpc/kvm/book3s_hv_interrupt.c:3:
arch/powerpc/kvm/book3s_hv_interrupt.c: In function 'switch_mmu_to_host_radix':
arch/powerpc/kvm/book3s_hv_interrupt.c:88:28: error: 'struct kvm_arch' has no member named 'host_lpid'
88 | mtspr(SPRN_LPID, kvm->arch.host_lpid);
| ^
arch/powerpc/include/asm/reg.h:1393:33: note: in definition of macro 'mtspr'
1393 | : "r" ((unsigned long)(v)) \
| ^
arch/powerpc/kvm/book3s_hv_interrupt.c:90:28: error: 'struct kvm_arch' has no member named 'host_lpcr'
90 | mtspr(SPRN_LPCR, kvm->arch.host_lpcr);
| ^
arch/powerpc/include/asm/reg.h:1393:33: note: in definition of macro 'mtspr'
1393 | : "r" ((unsigned long)(v)) \
| ^
arch/powerpc/kvm/book3s_hv_interrupt.c: At top level:
arch/powerpc/kvm/book3s_hv_interrupt.c:128:5: error: no previous prototype for 'kvmhv_vcpu_entry_p9' [-Werror=missing-prototypes]
128 | int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcr)
| ^~~~~~~~~~~~~~~~~~~
arch/powerpc/kvm/book3s_hv_interrupt.c: In function 'kvmhv_vcpu_entry_p9':
>> arch/powerpc/kvm/book3s_hv_interrupt.c:170:25: error: 'struct kvmppc_host_state' has no member named 'host_purr'; did you mean 'host_r1'?
170 | local_paca->kvm_hstate.host_purr = mfspr(SPRN_PURR);
| ^~~~~~~~~
| host_r1
>> arch/powerpc/kvm/book3s_hv_interrupt.c:171:25: error: 'struct kvmppc_host_state' has no member named 'host_spurr'; did you mean 'host_r1'?
171 | local_paca->kvm_hstate.host_spurr = mfspr(SPRN_SPURR);
| ^~~~~~~~~~
| host_r1
In file included from arch/powerpc/include/asm/processor.h:11,
from arch/powerpc/include/asm/thread_info.h:40,
from include/linux/thread_info.h:58,
from include/asm-generic/preempt.h:5,
from ./arch/powerpc/include/generated/asm/preempt.h:1,
from include/linux/preempt.h:78,
from include/linux/percpu.h:6,
from include/linux/context_tracking_state.h:5,
from include/linux/hardirq.h:5,
from include/linux/kvm_host.h:7,
from arch/powerpc/kvm/book3s_hv_interrupt.c:3:
>> arch/powerpc/kvm/book3s_hv_interrupt.c:187:31: error: 'struct kvmppc_host_state' has no member named 'fake_suspend'
187 | (local_paca->kvm_hstate.fake_suspend << PSSCR_FAKE_SUSPEND_LG));
| ^
arch/powerpc/include/asm/reg.h:1393:33: note: in definition of macro 'mtspr'
1393 | : "r" ((unsigned long)(v)) \
| ^
arch/powerpc/kvm/book3s_hv_interrupt.c:191:31: error: 'struct kvm_vcpu_arch' has no member named 'shregs'; did you mean 'regs'?
191 | mtspr(SPRN_SPRG0, vcpu->arch.shregs.sprg0);
| ^~~~~~
arch/powerpc/include/asm/reg.h:1393:33: note: in definition of macro 'mtspr'
1393 | : "r" ((unsigned long)(v)) \
| ^
arch/powerpc/kvm/book3s_hv_interrupt.c:192:31: error: 'struct kvm_vcpu_arch' has no member named 'shregs'; did you mean 'regs'?
192 | mtspr(SPRN_SPRG1, vcpu->arch.shregs.sprg1);
| ^~~~~~
arch/powerpc/include/asm/reg.h:1393:33: note: in definition of macro 'mtspr'
1393 | : "r" ((unsigned long)(v)) \
| ^
arch/powerpc/kvm/book3s_hv_interrupt.c:193:31: error: 'struct kvm_vcpu_arch' has no member named 'shregs'; did you mean 'regs'?
193 | mtspr(SPRN_SPRG2, vcpu->arch.shregs.sprg2);
| ^~~~~~
arch/powerpc/include/asm/reg.h:1393:33: note: in definition of macro 'mtspr'
1393 | : "r" ((unsigned long)(v)) \
| ^
arch/powerpc/kvm/book3s_hv_interrupt.c:194:31: error: 'struct kvm_vcpu_arch' has no member named 'shregs'; did you mean 'regs'?
194 | mtspr(SPRN_SPRG3, vcpu->arch.shregs.sprg3);
| ^~~~~~
arch/powerpc/include/asm/reg.h:1393:33: note: in definition of macro 'mtspr'
1393 | : "r" ((unsigned long)(v)) \
| ^
arch/powerpc/kvm/book3s_hv_interrupt.c:206:30: error: 'struct kvm_vcpu_arch' has no member named 'shregs'; did you mean 'regs'?
206 | mtspr(SPRN_SRR0, vcpu->arch.shregs.srr0);
| ^~~~~~
arch/powerpc/include/asm/reg.h:1393:33: note: in definition of macro 'mtspr'
1393 | : "r" ((unsigned long)(v)) \
| ^
arch/powerpc/kvm/book3s_hv_interrupt.c:207:30: error: 'struct kvm_vcpu_arch' has no member named 'shregs'; did you mean 'regs'?
207 | mtspr(SPRN_SRR1, vcpu->arch.shregs.srr1);
| ^~~~~~
arch/powerpc/include/asm/reg.h:1393:33: note: in definition of macro 'mtspr'
1393 | : "r" ((unsigned long)(v)) \
| ^
In file included from arch/powerpc/include/asm/bug.h:109,
from include/linux/bug.h:5,
from include/linux/mmdebug.h:5,
from include/linux/percpu.h:5,
from include/linux/context_tracking_state.h:5,
from include/linux/hardirq.h:5,
from include/linux/kvm_host.h:7,
from arch/powerpc/kvm/book3s_hv_interrupt.c:3:
arch/powerpc/kvm/book3s_hv_interrupt.c:213:26: error: 'struct kvm_vcpu_arch' has no member named 'shregs'; did you mean 'regs'?
213 | WARN_ON_ONCE(vcpu->arch.shregs.msr & MSR_HV);
| ^~~~~~
include/asm-generic/bug.h:102:25: note: in definition of macro 'WARN_ON_ONCE'
102 | int __ret_warn_on = !!(condition); \
| ^~~~~~~~~
arch/powerpc/kvm/book3s_hv_interrupt.c:214:28: error: 'struct kvm_vcpu_arch' has no member named 'shregs'; did you mean 'regs'?
214 | WARN_ON_ONCE(!(vcpu->arch.shregs.msr & MSR_ME));
| ^~~~~~
include/asm-generic/bug.h:102:25: note: in definition of macro 'WARN_ON_ONCE'
102 | int __ret_warn_on = !!(condition); \
| ^~~~~~~~~
In file included from arch/powerpc/include/asm/processor.h:11,
from arch/powerpc/include/asm/thread_info.h:40,
from include/linux/thread_info.h:58,
from include/asm-generic/preempt.h:5,
from ./arch/powerpc/include/generated/asm/preempt.h:1,
from include/linux/preempt.h:78,
from include/linux/percpu.h:6,
from include/linux/context_tracking_state.h:5,
from include/linux/hardirq.h:5,
from include/linux/kvm_host.h:7,
from arch/powerpc/kvm/book3s_hv_interrupt.c:3:
arch/powerpc/kvm/book3s_hv_interrupt.c:217:32: error: 'struct kvm_vcpu_arch' has no member named 'shregs'; did you mean 'regs'?
217 | mtspr(SPRN_HSRR1, (vcpu->arch.shregs.msr & ~MSR_HV) | MSR_ME);
| ^~~~~~
arch/powerpc/include/asm/reg.h:1393:33: note: in definition of macro 'mtspr'
1393 | : "r" ((unsigned long)(v)) \
| ^
arch/powerpc/kvm/book3s_hv_interrupt.c:244:13: error: 'struct kvm_vcpu_arch' has no member named 'shregs'; did you mean 'regs'?
244 | vcpu->arch.shregs.srr0 = mfspr(SPRN_SRR0);
| ^~~~~~
| regs
arch/powerpc/kvm/book3s_hv_interrupt.c:245:13: error: 'struct kvm_vcpu_arch' has no member named 'shregs'; did you mean 'regs'?
245 | vcpu->arch.shregs.srr1 = mfspr(SPRN_SRR1);
| ^~~~~~
| regs
arch/powerpc/kvm/book3s_hv_interrupt.c:246:13: error: 'struct kvm_vcpu_arch' has no member named 'shregs'; did you mean 'regs'?
246 | vcpu->arch.shregs.dar = mfspr(SPRN_DAR);
| ^~~~~~
| regs
arch/powerpc/kvm/book3s_hv_interrupt.c:247:13: error: 'struct kvm_vcpu_arch' has no member named 'shregs'; did you mean 'regs'?
247 | vcpu->arch.shregs.dsisr = mfspr(SPRN_DSISR);
| ^~~~~~
| regs
arch/powerpc/kvm/book3s_hv_interrupt.c:281:13: error: 'struct kvm_vcpu_arch' has no member named 'emul_inst'
281 | vcpu->arch.emul_inst = mfspr(SPRN_HEIR);
| ^
In file included from arch/powerpc/include/asm/processor.h:11,
from arch/powerpc/include/asm/thread_info.h:40,
from include/linux/thread_info.h:58,
vim +170 arch/powerpc/kvm/book3s_hv_interrupt.c
127
128 int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcr)
129 {
130 struct kvm *kvm = vcpu->kvm;
131 struct kvmppc_vcore *vc = vcpu->arch.vcore;
132 s64 hdec;
133 u64 tb, purr, spurr;
134 u64 *exsave;
135 unsigned long msr = mfmsr();
136 int trap;
137 unsigned long host_hfscr = mfspr(SPRN_HFSCR);
138 unsigned long host_ciabr = mfspr(SPRN_CIABR);
139 unsigned long host_dawr0 = mfspr(SPRN_DAWR0);
140 unsigned long host_dawrx0 = mfspr(SPRN_DAWRX0);
141 unsigned long host_psscr = mfspr(SPRN_PSSCR);
142 unsigned long host_pidr = mfspr(SPRN_PID);
143 unsigned long host_dawr1 = 0;
144 unsigned long host_dawrx1 = 0;
145
146 if (cpu_has_feature(CPU_FTR_DAWR1)) {
147 host_dawr1 = mfspr(SPRN_DAWR1);
148 host_dawrx1 = mfspr(SPRN_DAWRX1);
149 }
150
151 tb = mftb();
152 hdec = time_limit - tb;
153 if (hdec < 0)
154 return BOOK3S_INTERRUPT_HV_DECREMENTER;
155
156 if (vc->tb_offset) {
157 u64 new_tb = tb + vc->tb_offset;
158 mtspr(SPRN_TBU40, new_tb);
159 tb = mftb();
160 if ((tb & 0xffffff) < (new_tb & 0xffffff))
161 mtspr(SPRN_TBU40, new_tb + 0x1000000);
162 vc->tb_offset_applied = vc->tb_offset;
163 }
164
165 if (vc->pcr)
166 mtspr(SPRN_PCR, vc->pcr | PCR_MASK);
167 mtspr(SPRN_DPDES, vc->dpdes);
168 mtspr(SPRN_VTB, vc->vtb);
169
> 170 local_paca->kvm_hstate.host_purr = mfspr(SPRN_PURR);
> 171 local_paca->kvm_hstate.host_spurr = mfspr(SPRN_SPURR);
172 mtspr(SPRN_PURR, vcpu->arch.purr);
173 mtspr(SPRN_SPURR, vcpu->arch.spurr);
174
175 if (dawr_enabled()) {
176 mtspr(SPRN_DAWR0, vcpu->arch.dawr0);
177 mtspr(SPRN_DAWRX0, vcpu->arch.dawrx0);
178 if (cpu_has_feature(CPU_FTR_DAWR1)) {
179 mtspr(SPRN_DAWR1, vcpu->arch.dawr1);
180 mtspr(SPRN_DAWRX1, vcpu->arch.dawrx1);
181 }
182 }
183 mtspr(SPRN_CIABR, vcpu->arch.ciabr);
184 mtspr(SPRN_IC, vcpu->arch.ic);
185
186 mtspr(SPRN_PSSCR, vcpu->arch.psscr | PSSCR_EC |
> 187 (local_paca->kvm_hstate.fake_suspend << PSSCR_FAKE_SUSPEND_LG));
188
189 mtspr(SPRN_HFSCR, vcpu->arch.hfscr);
190
191 mtspr(SPRN_SPRG0, vcpu->arch.shregs.sprg0);
192 mtspr(SPRN_SPRG1, vcpu->arch.shregs.sprg1);
193 mtspr(SPRN_SPRG2, vcpu->arch.shregs.sprg2);
194 mtspr(SPRN_SPRG3, vcpu->arch.shregs.sprg3);
195
196 mtspr(SPRN_AMOR, ~0UL);
197
198 switch_mmu_to_guest_radix(kvm, vcpu, lpcr);
199
200 /*
201 * P9 suppresses the HDEC exception when LPCR[HDICE] = 0,
202 * so set guest LPCR (with HDICE) before writing HDEC.
203 */
204 mtspr(SPRN_HDEC, hdec);
205
206 mtspr(SPRN_SRR0, vcpu->arch.shregs.srr0);
207 mtspr(SPRN_SRR1, vcpu->arch.shregs.srr1);
208
209 start_timing(vcpu, &vcpu->arch.rm_entry);
210
211 vcpu->arch.ceded = 0;
212
213 WARN_ON_ONCE(vcpu->arch.shregs.msr & MSR_HV);
214 WARN_ON_ONCE(!(vcpu->arch.shregs.msr & MSR_ME));
215
216 mtspr(SPRN_HSRR0, vcpu->arch.regs.nip);
217 mtspr(SPRN_HSRR1, (vcpu->arch.shregs.msr & ~MSR_HV) | MSR_ME);
218
219 /*
220 * On POWER9 DD2.1 and below, sometimes on a Hypervisor Data Storage
221 * Interrupt (HDSI) the HDSISR is not be updated at all.
222 *
223 * To work around this we put a canary value into the HDSISR before
224 * returning to a guest and then check for this canary when we take a
225 * HDSI. If we find the canary on a HDSI, we know the hardware didn't
226 * update the HDSISR. In this case we return to the guest to retake the
227 * HDSI which should correctly update the HDSISR the second time HDSI
228 * entry.
229 *
230 * Just do this on all p9 processors for now.
231 */
232 mtspr(SPRN_HDSISR, HDSISR_CANARY);
233
234 accumulate_time(vcpu, &vcpu->arch.guest_time);
235
236 local_paca->kvm_hstate.in_guest = KVM_GUEST_MODE_GUEST_HV_FAST;
237 kvmppc_p9_enter_guest(vcpu);
238 // Radix host and guest means host never runs with guest MMU state
239 local_paca->kvm_hstate.in_guest = KVM_GUEST_MODE_NONE;
240
241 accumulate_time(vcpu, &vcpu->arch.rm_intr);
242
243 /* Get these from r11/12 and paca exsave */
244 vcpu->arch.shregs.srr0 = mfspr(SPRN_SRR0);
245 vcpu->arch.shregs.srr1 = mfspr(SPRN_SRR1);
246 vcpu->arch.shregs.dar = mfspr(SPRN_DAR);
247 vcpu->arch.shregs.dsisr = mfspr(SPRN_DSISR);
248
249 /* 0x2 bit for HSRR is only used by PR and P7/8 HV paths, clear it */
250 trap = local_paca->kvm_hstate.scratch0 & ~0x2;
251 if (likely(trap > BOOK3S_INTERRUPT_MACHINE_CHECK)) {
252 exsave = local_paca->exgen;
253 } else if (trap == BOOK3S_INTERRUPT_SYSTEM_RESET) {
254 exsave = local_paca->exnmi;
255 } else { /* trap == 0x200 */
256 exsave = local_paca->exmc;
257 }
258
259 vcpu->arch.regs.gpr[1] = local_paca->kvm_hstate.scratch1;
260 vcpu->arch.regs.gpr[3] = local_paca->kvm_hstate.scratch2;
261 vcpu->arch.regs.gpr[9] = exsave[EX_R9/sizeof(u64)];
262 vcpu->arch.regs.gpr[10] = exsave[EX_R10/sizeof(u64)];
263 vcpu->arch.regs.gpr[11] = exsave[EX_R11/sizeof(u64)];
264 vcpu->arch.regs.gpr[12] = exsave[EX_R12/sizeof(u64)];
265 vcpu->arch.regs.gpr[13] = exsave[EX_R13/sizeof(u64)];
266 vcpu->arch.ppr = exsave[EX_PPR/sizeof(u64)];
267 vcpu->arch.cfar = exsave[EX_CFAR/sizeof(u64)];
268 vcpu->arch.regs.ctr = exsave[EX_CTR/sizeof(u64)];
269
270 vcpu->arch.last_inst = KVM_INST_FETCH_FAILED;
271
272 if (unlikely(trap == BOOK3S_INTERRUPT_MACHINE_CHECK)) {
273 vcpu->arch.fault_dar = exsave[EX_DAR/sizeof(u64)];
274 vcpu->arch.fault_dsisr = exsave[EX_DSISR/sizeof(u64)];
275 kvmppc_realmode_machine_check(vcpu);
276
277 } else if (unlikely(trap == BOOK3S_INTERRUPT_HMI)) {
278 kvmppc_realmode_hmi_handler();
279
280 } else if (trap == BOOK3S_INTERRUPT_H_EMUL_ASSIST) {
281 vcpu->arch.emul_inst = mfspr(SPRN_HEIR);
282
283 } else if (trap == BOOK3S_INTERRUPT_H_DATA_STORAGE) {
284 vcpu->arch.fault_dar = exsave[EX_DAR/sizeof(u64)];
285 vcpu->arch.fault_dsisr = exsave[EX_DSISR/sizeof(u64)];
286 vcpu->arch.fault_gpa = mfspr(SPRN_ASDR);
287
288 } else if (trap == BOOK3S_INTERRUPT_H_INST_STORAGE) {
289 vcpu->arch.fault_gpa = mfspr(SPRN_ASDR);
290
291 } else if (trap == BOOK3S_INTERRUPT_H_FAC_UNAVAIL) {
292 vcpu->arch.hfscr = mfspr(SPRN_HFSCR);
293
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
diff --git a/arch/powerpc/include/asm/kvm_book3s_64.h b/arch/powerpc/include/asm/kvm_book3s_64.h index c214bcffb441..eaf3a562bf1e 100644 --- a/arch/powerpc/include/asm/kvm_book3s_64.h +++ b/arch/powerpc/include/asm/kvm_book3s_64.h @@ -153,7 +153,7 @@ static inline bool kvmhv_vcpu_is_radix(struct kvm_vcpu *vcpu) return radix; } -int __kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu); +int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcr); #define KVM_DEFAULT_HPT_ORDER 24 /* 16MB HPT by default */ #endif diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c index e579b935ead0..af0eedcaab8b 100644 --- a/arch/powerpc/kvm/book3s_hv.c +++ b/arch/powerpc/kvm/book3s_hv.c @@ -3492,194 +3492,6 @@ static noinline void kvmppc_run_core(struct kvmppc_vcore *vc) trace_kvmppc_run_core(vc, 1); } -static void switch_mmu_to_guest_radix(struct kvm *kvm, struct kvm_vcpu *vcpu, u64 lpcr) -{ - struct kvmppc_vcore *vc = vcpu->arch.vcore; - struct kvm_nested_guest *nested = vcpu->arch.nested; - u32 lpid; - - lpid = nested ? nested->shadow_lpid : kvm->arch.lpid; - - /* - * All the isync()s are overkill but trivially follow the ISA - * requirements. Some can likely be replaced with justification - * comment for why they are not needed. - */ - isync(); - mtspr(SPRN_LPID, lpid); - isync(); - mtspr(SPRN_LPCR, lpcr); - isync(); - mtspr(SPRN_PID, vcpu->arch.pid); - isync(); - - /* TLBIEL must have LPIDR set, so set guest LPID before flushing. */ - kvmppc_check_need_tlb_flush(kvm, vc->pcpu, nested); -} - -static void switch_mmu_to_host_radix(struct kvm *kvm, u32 pid) -{ - isync(); - mtspr(SPRN_PID, pid); - isync(); - mtspr(SPRN_LPID, kvm->arch.host_lpid); - isync(); - mtspr(SPRN_LPCR, kvm->arch.host_lpcr); - isync(); -} - -/* - * Load up hypervisor-mode registers on P9. - */ -static int kvmhv_load_hv_regs_and_go(struct kvm_vcpu *vcpu, u64 time_limit, - unsigned long lpcr) -{ - struct kvm *kvm = vcpu->kvm; - struct kvmppc_vcore *vc = vcpu->arch.vcore; - s64 hdec; - u64 tb, purr, spurr; - int trap; - unsigned long host_hfscr = mfspr(SPRN_HFSCR); - unsigned long host_ciabr = mfspr(SPRN_CIABR); - unsigned long host_dawr0 = mfspr(SPRN_DAWR0); - unsigned long host_dawrx0 = mfspr(SPRN_DAWRX0); - unsigned long host_psscr = mfspr(SPRN_PSSCR); - unsigned long host_pidr = mfspr(SPRN_PID); - unsigned long host_dawr1 = 0; - unsigned long host_dawrx1 = 0; - - if (cpu_has_feature(CPU_FTR_DAWR1)) { - host_dawr1 = mfspr(SPRN_DAWR1); - host_dawrx1 = mfspr(SPRN_DAWRX1); - } - - tb = mftb(); - hdec = time_limit - tb; - if (hdec < 0) - return BOOK3S_INTERRUPT_HV_DECREMENTER; - - if (vc->tb_offset) { - u64 new_tb = tb + vc->tb_offset; - mtspr(SPRN_TBU40, new_tb); - tb = mftb(); - if ((tb & 0xffffff) < (new_tb & 0xffffff)) - mtspr(SPRN_TBU40, new_tb + 0x1000000); - vc->tb_offset_applied = vc->tb_offset; - } - - if (vc->pcr) - mtspr(SPRN_PCR, vc->pcr | PCR_MASK); - mtspr(SPRN_DPDES, vc->dpdes); - mtspr(SPRN_VTB, vc->vtb); - - local_paca->kvm_hstate.host_purr = mfspr(SPRN_PURR); - local_paca->kvm_hstate.host_spurr = mfspr(SPRN_SPURR); - mtspr(SPRN_PURR, vcpu->arch.purr); - mtspr(SPRN_SPURR, vcpu->arch.spurr); - - if (dawr_enabled()) { - mtspr(SPRN_DAWR0, vcpu->arch.dawr0); - mtspr(SPRN_DAWRX0, vcpu->arch.dawrx0); - if (cpu_has_feature(CPU_FTR_DAWR1)) { - mtspr(SPRN_DAWR1, vcpu->arch.dawr1); - mtspr(SPRN_DAWRX1, vcpu->arch.dawrx1); - } - } - mtspr(SPRN_CIABR, vcpu->arch.ciabr); - mtspr(SPRN_IC, vcpu->arch.ic); - - mtspr(SPRN_PSSCR, vcpu->arch.psscr | PSSCR_EC | - (local_paca->kvm_hstate.fake_suspend << PSSCR_FAKE_SUSPEND_LG)); - - mtspr(SPRN_HFSCR, vcpu->arch.hfscr); - - mtspr(SPRN_SPRG0, vcpu->arch.shregs.sprg0); - mtspr(SPRN_SPRG1, vcpu->arch.shregs.sprg1); - mtspr(SPRN_SPRG2, vcpu->arch.shregs.sprg2); - mtspr(SPRN_SPRG3, vcpu->arch.shregs.sprg3); - - mtspr(SPRN_AMOR, ~0UL); - - switch_mmu_to_guest_radix(kvm, vcpu, lpcr); - - /* - * P9 suppresses the HDEC exception when LPCR[HDICE] = 0, - * so set guest LPCR (with HDICE) before writing HDEC. - */ - mtspr(SPRN_HDEC, hdec); - - mtspr(SPRN_SRR0, vcpu->arch.shregs.srr0); - mtspr(SPRN_SRR1, vcpu->arch.shregs.srr1); - - trap = __kvmhv_vcpu_entry_p9(vcpu); - - /* Advance host PURR/SPURR by the amount used by guest */ - purr = mfspr(SPRN_PURR); - spurr = mfspr(SPRN_SPURR); - mtspr(SPRN_PURR, local_paca->kvm_hstate.host_purr + - purr - vcpu->arch.purr); - mtspr(SPRN_SPURR, local_paca->kvm_hstate.host_spurr + - spurr - vcpu->arch.spurr); - vcpu->arch.purr = purr; - vcpu->arch.spurr = spurr; - - vcpu->arch.ic = mfspr(SPRN_IC); - vcpu->arch.pid = mfspr(SPRN_PID); - vcpu->arch.psscr = mfspr(SPRN_PSSCR) & PSSCR_GUEST_VIS; - - vcpu->arch.shregs.sprg0 = mfspr(SPRN_SPRG0); - vcpu->arch.shregs.sprg1 = mfspr(SPRN_SPRG1); - vcpu->arch.shregs.sprg2 = mfspr(SPRN_SPRG2); - vcpu->arch.shregs.sprg3 = mfspr(SPRN_SPRG3); - - /* Preserve PSSCR[FAKE_SUSPEND] until we've called kvmppc_save_tm_hv */ - mtspr(SPRN_PSSCR, host_psscr | - (local_paca->kvm_hstate.fake_suspend << PSSCR_FAKE_SUSPEND_LG)); - mtspr(SPRN_HFSCR, host_hfscr); - mtspr(SPRN_CIABR, host_ciabr); - mtspr(SPRN_DAWR0, host_dawr0); - mtspr(SPRN_DAWRX0, host_dawrx0); - if (cpu_has_feature(CPU_FTR_DAWR1)) { - mtspr(SPRN_DAWR1, host_dawr1); - mtspr(SPRN_DAWRX1, host_dawrx1); - } - - /* - * Since this is radix, do a eieio; tlbsync; ptesync sequence in - * case we interrupted the guest between a tlbie and a ptesync. - */ - asm volatile("eieio; tlbsync; ptesync"); - - /* - * cp_abort is required if the processor supports local copy-paste - * to clear the copy buffer that was under control of the guest. - */ - if (cpu_has_feature(CPU_FTR_ARCH_31)) - asm volatile(PPC_CP_ABORT); - - vc->dpdes = mfspr(SPRN_DPDES); - vc->vtb = mfspr(SPRN_VTB); - mtspr(SPRN_DPDES, 0); - if (vc->pcr) - mtspr(SPRN_PCR, PCR_MASK); - - if (vc->tb_offset_applied) { - u64 new_tb = mftb() - vc->tb_offset_applied; - mtspr(SPRN_TBU40, new_tb); - tb = mftb(); - if ((tb & 0xffffff) < (new_tb & 0xffffff)) - mtspr(SPRN_TBU40, new_tb + 0x1000000); - vc->tb_offset_applied = 0; - } - - /* HDEC must be at least as large as DEC, so decrementer_max fits */ - mtspr(SPRN_HDEC, decrementer_max); - - switch_mmu_to_host_radix(kvm, host_pidr); - - return trap; -} - static inline bool hcall_is_xics(unsigned long req) { return req == H_EOI || req == H_CPPR || req == H_IPI || @@ -3776,7 +3588,7 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit, * We need to save and restore the guest visible part of the * psscr (i.e. using SPRN_PSSCR_PR) since the hypervisor * doesn't do this for us. Note only required if pseries since - * this is done in kvmhv_load_hv_regs_and_go() below otherwise. + * this is done in kvmhv_vcpu_entry_p9() below otherwise. */ unsigned long host_psscr; /* call our hypervisor to load up HV regs and go */ @@ -3814,7 +3626,7 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit, } } else { kvmppc_xive_push_vcpu(vcpu); - trap = kvmhv_load_hv_regs_and_go(vcpu, time_limit, lpcr); + trap = kvmhv_vcpu_entry_p9(vcpu, time_limit, lpcr); if (trap == BOOK3S_INTERRUPT_SYSCALL && !vcpu->arch.nested && !(vcpu->arch.shregs.msr & MSR_PR)) { unsigned long req = kvmppc_get_gpr(vcpu, 3); diff --git a/arch/powerpc/kvm/book3s_hv_interrupt.c b/arch/powerpc/kvm/book3s_hv_interrupt.c index 69f861cf3b90..15f1b78c5c90 100644 --- a/arch/powerpc/kvm/book3s_hv_interrupt.c +++ b/arch/powerpc/kvm/book3s_hv_interrupt.c @@ -55,6 +55,42 @@ static void __accumulate_time(struct kvm_vcpu *vcpu, struct kvmhv_tb_accumulator #define accumulate_time(vcpu, next) do {} while (0) #endif +static void switch_mmu_to_guest_radix(struct kvm *kvm, struct kvm_vcpu *vcpu, u64 lpcr) +{ + struct kvmppc_vcore *vc = vcpu->arch.vcore; + struct kvm_nested_guest *nested = vcpu->arch.nested; + u32 lpid; + + lpid = nested ? nested->shadow_lpid : kvm->arch.lpid; + + /* + * All the isync()s are overkill but trivially follow the ISA + * requirements. Some can likely be replaced with justification + * comment for why they are not needed. + */ + isync(); + mtspr(SPRN_LPID, lpid); + isync(); + mtspr(SPRN_LPCR, lpcr); + isync(); + mtspr(SPRN_PID, vcpu->arch.pid); + isync(); + + /* TLBIEL must have LPIDR set, so set guest LPID before flushing. */ + kvmppc_check_need_tlb_flush(kvm, vc->pcpu, nested); +} + +static void switch_mmu_to_host_radix(struct kvm *kvm, u32 pid) +{ + isync(); + mtspr(SPRN_PID, pid); + isync(); + mtspr(SPRN_LPID, kvm->arch.host_lpid); + isync(); + mtspr(SPRN_LPCR, kvm->arch.host_lpcr); + isync(); +} + static inline void mfslb(unsigned int idx, u64 *slbee, u64 *slbev) { asm volatile("slbmfev %0,%1" : "=r" (*slbev) : "r" (idx)); @@ -89,11 +125,86 @@ static void radix_clear_slb(void) } } -int __kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu) +int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcr) { + struct kvm *kvm = vcpu->kvm; + struct kvmppc_vcore *vc = vcpu->arch.vcore; + s64 hdec; + u64 tb, purr, spurr; u64 *exsave; unsigned long msr = mfmsr(); int trap; + unsigned long host_hfscr = mfspr(SPRN_HFSCR); + unsigned long host_ciabr = mfspr(SPRN_CIABR); + unsigned long host_dawr0 = mfspr(SPRN_DAWR0); + unsigned long host_dawrx0 = mfspr(SPRN_DAWRX0); + unsigned long host_psscr = mfspr(SPRN_PSSCR); + unsigned long host_pidr = mfspr(SPRN_PID); + unsigned long host_dawr1 = 0; + unsigned long host_dawrx1 = 0; + + if (cpu_has_feature(CPU_FTR_DAWR1)) { + host_dawr1 = mfspr(SPRN_DAWR1); + host_dawrx1 = mfspr(SPRN_DAWRX1); + } + + tb = mftb(); + hdec = time_limit - tb; + if (hdec < 0) + return BOOK3S_INTERRUPT_HV_DECREMENTER; + + if (vc->tb_offset) { + u64 new_tb = tb + vc->tb_offset; + mtspr(SPRN_TBU40, new_tb); + tb = mftb(); + if ((tb & 0xffffff) < (new_tb & 0xffffff)) + mtspr(SPRN_TBU40, new_tb + 0x1000000); + vc->tb_offset_applied = vc->tb_offset; + } + + if (vc->pcr) + mtspr(SPRN_PCR, vc->pcr | PCR_MASK); + mtspr(SPRN_DPDES, vc->dpdes); + mtspr(SPRN_VTB, vc->vtb); + + local_paca->kvm_hstate.host_purr = mfspr(SPRN_PURR); + local_paca->kvm_hstate.host_spurr = mfspr(SPRN_SPURR); + mtspr(SPRN_PURR, vcpu->arch.purr); + mtspr(SPRN_SPURR, vcpu->arch.spurr); + + if (dawr_enabled()) { + mtspr(SPRN_DAWR0, vcpu->arch.dawr0); + mtspr(SPRN_DAWRX0, vcpu->arch.dawrx0); + if (cpu_has_feature(CPU_FTR_DAWR1)) { + mtspr(SPRN_DAWR1, vcpu->arch.dawr1); + mtspr(SPRN_DAWRX1, vcpu->arch.dawrx1); + } + } + mtspr(SPRN_CIABR, vcpu->arch.ciabr); + mtspr(SPRN_IC, vcpu->arch.ic); + + mtspr(SPRN_PSSCR, vcpu->arch.psscr | PSSCR_EC | + (local_paca->kvm_hstate.fake_suspend << PSSCR_FAKE_SUSPEND_LG)); + + mtspr(SPRN_HFSCR, vcpu->arch.hfscr); + + mtspr(SPRN_SPRG0, vcpu->arch.shregs.sprg0); + mtspr(SPRN_SPRG1, vcpu->arch.shregs.sprg1); + mtspr(SPRN_SPRG2, vcpu->arch.shregs.sprg2); + mtspr(SPRN_SPRG3, vcpu->arch.shregs.sprg3); + + mtspr(SPRN_AMOR, ~0UL); + + switch_mmu_to_guest_radix(kvm, vcpu, lpcr); + + /* + * P9 suppresses the HDEC exception when LPCR[HDICE] = 0, + * so set guest LPCR (with HDICE) before writing HDEC. + */ + mtspr(SPRN_HDEC, hdec); + + mtspr(SPRN_SRR0, vcpu->arch.shregs.srr0); + mtspr(SPRN_SRR1, vcpu->arch.shregs.srr1); start_timing(vcpu, &vcpu->arch.rm_entry); @@ -213,6 +324,70 @@ int __kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu) end_timing(vcpu); + /* Advance host PURR/SPURR by the amount used by guest */ + purr = mfspr(SPRN_PURR); + spurr = mfspr(SPRN_SPURR); + mtspr(SPRN_PURR, local_paca->kvm_hstate.host_purr + + purr - vcpu->arch.purr); + mtspr(SPRN_SPURR, local_paca->kvm_hstate.host_spurr + + spurr - vcpu->arch.spurr); + vcpu->arch.purr = purr; + vcpu->arch.spurr = spurr; + + vcpu->arch.ic = mfspr(SPRN_IC); + vcpu->arch.pid = mfspr(SPRN_PID); + vcpu->arch.psscr = mfspr(SPRN_PSSCR) & PSSCR_GUEST_VIS; + + vcpu->arch.shregs.sprg0 = mfspr(SPRN_SPRG0); + vcpu->arch.shregs.sprg1 = mfspr(SPRN_SPRG1); + vcpu->arch.shregs.sprg2 = mfspr(SPRN_SPRG2); + vcpu->arch.shregs.sprg3 = mfspr(SPRN_SPRG3); + + /* Preserve PSSCR[FAKE_SUSPEND] until we've called kvmppc_save_tm_hv */ + mtspr(SPRN_PSSCR, host_psscr | + (local_paca->kvm_hstate.fake_suspend << PSSCR_FAKE_SUSPEND_LG)); + mtspr(SPRN_HFSCR, host_hfscr); + mtspr(SPRN_CIABR, host_ciabr); + mtspr(SPRN_DAWR0, host_dawr0); + mtspr(SPRN_DAWRX0, host_dawrx0); + if (cpu_has_feature(CPU_FTR_DAWR1)) { + mtspr(SPRN_DAWR1, host_dawr1); + mtspr(SPRN_DAWRX1, host_dawrx1); + } + + /* + * Since this is radix, do a eieio; tlbsync; ptesync sequence in + * case we interrupted the guest between a tlbie and a ptesync. + */ + asm volatile("eieio; tlbsync; ptesync"); + + /* + * cp_abort is required if the processor supports local copy-paste + * to clear the copy buffer that was under control of the guest. + */ + if (cpu_has_feature(CPU_FTR_ARCH_31)) + asm volatile(PPC_CP_ABORT); + + vc->dpdes = mfspr(SPRN_DPDES); + vc->vtb = mfspr(SPRN_VTB); + mtspr(SPRN_DPDES, 0); + if (vc->pcr) + mtspr(SPRN_PCR, PCR_MASK); + + if (vc->tb_offset_applied) { + u64 new_tb = mftb() - vc->tb_offset_applied; + mtspr(SPRN_TBU40, new_tb); + tb = mftb(); + if ((tb & 0xffffff) < (new_tb & 0xffffff)) + mtspr(SPRN_TBU40, new_tb + 0x1000000); + vc->tb_offset_applied = 0; + } + + /* HDEC must be at least as large as DEC, so decrementer_max fits */ + mtspr(SPRN_HDEC, decrementer_max); + + switch_mmu_to_host_radix(kvm, host_pidr); + return trap; } -EXPORT_SYMBOL_GPL(__kvmhv_vcpu_entry_p9); +EXPORT_SYMBOL_GPL(kvmhv_vcpu_entry_p9);