From patchwork Tue Jan 22 15:59:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ram Pai X-Patchwork-Id: 1029370 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43kY6g4Gx4z9sBn for ; Wed, 23 Jan 2019 03:00:43 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728673AbfAVQAm (ORCPT ); Tue, 22 Jan 2019 11:00:42 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:8583 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728784AbfAVQAm (ORCPT ); Tue, 22 Jan 2019 11:00:42 -0500 Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x0MFvaUT040790 for ; Tue, 22 Jan 2019 11:00:41 -0500 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0a-001b2d01.pphosted.com with ESMTP id 2q6421y7fp-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 22 Jan 2019 11:00:38 -0500 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 22 Jan 2019 16:00:24 -0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x0MG0MPW42664088 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Jan 2019 16:00:22 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E40C4A406F; Tue, 22 Jan 2019 16:00:21 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 24228A407C; Tue, 22 Jan 2019 16:00:18 +0000 (GMT) Received: from ram.ibm.com (unknown [9.85.201.166]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 22 Jan 2019 16:00:17 +0000 (GMT) From: Ram Pai To: kvm-ppc@vger.kernel.org Cc: cclaudio@br.ibm.com, maddy@linux.vnet.ibm.com, rgrimm@us.ibm.com, pmac@au1.ibm.com, andmike@us.ibm.com, sukadev@linux.vnet.ibm.com, bauerman@linux.ibm.com, santosh@linux.ibm.com, benh@linux.ibm.com, sesmith@au1.ibm.com, bharata@linux.ibm.com Subject: [PATCH 03/13] KVM: PPC: Ultravisor: Introduce the MSR_S bit Date: Tue, 22 Jan 2019 07:59:34 -0800 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1548172784-27414-3-git-send-email-linuxram@us.ibm.com> References: <1548172784-27414-1-git-send-email-linuxram@us.ibm.com> <1548172784-27414-2-git-send-email-linuxram@us.ibm.com> <1548172784-27414-3-git-send-email-linuxram@us.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 19012216-0016-0000-0000-00000248E385 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19012216-0017-0000-0000-000032A31CB0 Message-Id: <1548172784-27414-4-git-send-email-linuxram@us.ibm.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-22_08:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=454 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901220124 Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Sukadev Bhattiprolu MSR_S bit enables access to secure memory. Signed-off-by: Ram Pai Signed-off-by: Sukadev Bhattiprolu --- arch/powerpc/include/asm/reg.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 1c98ef1..3c3588a 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -38,6 +38,7 @@ #define MSR_TM_LG 32 /* Trans Mem Available */ #define MSR_VEC_LG 25 /* Enable AltiVec */ #define MSR_VSX_LG 23 /* Enable VSX */ +#define MSR_S_LG 22 /* Secure VM bit */ #define MSR_POW_LG 18 /* Enable Power Management */ #define MSR_WE_LG 18 /* Wait State Enable */ #define MSR_TGPR_LG 17 /* TLB Update registers in use */ @@ -71,11 +72,13 @@ #define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */ #define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */ #define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */ +#define MSR_S __MASK(MSR_S_LG) /* Secure state */ #else /* so tests for these bits fail on 32-bit */ #define MSR_SF 0 #define MSR_ISF 0 #define MSR_HV 0 +#define MSR_S 0 #endif /*