@@ -1119,8 +1119,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
mfspr r6, SPRN_HSRR1
andis. r6, r6, MSR_S@high
- cmplwi r6, 0
- bne ret_to_ultra;
+ bne ret_to_ultra
lwz r6, VCPU_CR(r4)
mtcr r6
@@ -1140,6 +1139,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
ret_to_ultra:
lwz r6, VCPU_CR(r4)
mtcr r6
+ mfspr r11, SPRN_SRR1
LOAD_REG_IMMEDIATE(r0, UV_RETURN)
ld r6, VCPU_GPR(R6)(r4)
ld r4, VCPU_GPR(R4)(r4)
@@ -3344,13 +3344,16 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
* r0 is used as a scratch register
*/
kvmppc_msr_interrupt:
+ andis. r0, r11, MSR_S@h
rldicl r0, r11, 64 - MSR_TS_S_LG, 62
- cmpwi r0, 2 /* Check if we are in transactional state.. */
+ cmpwi cr1, r0, 2 /* Check if we are in transactional state.. */
ld r11, VCPU_INTR_MSR(r9)
- bne 1f
+ bne cr1, 1f
/* ... if transactional, change to suspended */
li r0, 1
1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
+ beqlr
+ oris r11, r11, MSR_S@h /* preserve MSR_S bit setting */
blr
/*