diff mbox series

[3/3] Revert "e1000e: Add handshake with the CSME to support S0ix"

Message ID 20211122161927.874291-3-kai.heng.feng@canonical.com
State Rejected
Headers show
Series [1/3] Revert "e1000e: Additional PHY power saving in S0ix" | expand

Commit Message

Kai-Heng Feng Nov. 22, 2021, 4:19 p.m. UTC
This reverts commit 3e55d231716ea361b1520b801c6778c4c48de102.

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=214821
Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
---
 drivers/net/ethernet/intel/e1000e/ich8lan.h |   2 -
 drivers/net/ethernet/intel/e1000e/netdev.c  | 328 +++++++++-----------
 2 files changed, 154 insertions(+), 176 deletions(-)

Comments

Neftin, Sasha Nov. 28, 2021, 1:23 p.m. UTC | #1
On 11/22/2021 18:19, Kai-Heng Feng wrote:
> This reverts commit 3e55d231716ea361b1520b801c6778c4c48de102.
> 
> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=214821
> Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
> ---
>   drivers/net/ethernet/intel/e1000e/ich8lan.h |   2 -
>   drivers/net/ethernet/intel/e1000e/netdev.c  | 328 +++++++++-----------
>   2 files changed, 154 insertions(+), 176 deletions(-)
> 
> diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.h b/drivers/net/ethernet/intel/e1000e/ich8lan.h
> index 1dfa1d28dae64..8f2a8f4ce0ee4 100644
> --- a/drivers/net/ethernet/intel/e1000e/ich8lan.h
> +++ b/drivers/net/ethernet/intel/e1000e/ich8lan.h
> @@ -47,8 +47,6 @@
>   #define E1000_SHRAH_PCH_LPT(_i)		(0x0540C + ((_i) * 8))
>   
>   #define E1000_H2ME		0x05B50	/* Host to ME */
> -#define E1000_H2ME_START_DPG	0x00000001	/* indicate the ME of DPG */
> -#define E1000_H2ME_EXIT_DPG	0x00000002	/* indicate the ME exit DPG */
>   #define E1000_H2ME_ULP		0x00000800	/* ULP Indication Bit */
>   #define E1000_H2ME_ENFORCE_SETTINGS	0x00001000	/* Enforce Settings */
>   
> diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c
> index 242314809e59c..52c91c52b971b 100644
> --- a/drivers/net/ethernet/intel/e1000e/netdev.c
> +++ b/drivers/net/ethernet/intel/e1000e/netdev.c
> @@ -6345,105 +6345,43 @@ static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter)
>   	u32 mac_data;
>   	u16 phy_data;
>   
> -	if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
> -		/* Request ME configure the device for S0ix */
> -		mac_data = er32(H2ME);
> -		mac_data |= E1000_H2ME_START_DPG;
> -		mac_data &= ~E1000_H2ME_EXIT_DPG;
> -		ew32(H2ME, mac_data);
> -	} else {
> -		/* Request driver configure the device to S0ix */
> -		/* Disable the periodic inband message,
> -		 * don't request PCIe clock in K1 page770_17[10:9] = 10b
> -		 */
> -		e1e_rphy(hw, HV_PM_CTRL, &phy_data);
> -		phy_data &= ~HV_PM_CTRL_K1_CLK_REQ;
> -		phy_data |= BIT(10);
> -		e1e_wphy(hw, HV_PM_CTRL, phy_data);
> -
> -		/* Make sure we don't exit K1 every time a new packet arrives
> -		 * 772_29[5] = 1 CS_Mode_Stay_In_K1
> -		 */
> -		e1e_rphy(hw, I217_CGFREG, &phy_data);
> -		phy_data |= BIT(5);
> -		e1e_wphy(hw, I217_CGFREG, phy_data);
> -
> -		/* Change the MAC/PHY interface to SMBus
> -		 * Force the SMBus in PHY page769_23[0] = 1
> -		 * Force the SMBus in MAC CTRL_EXT[11] = 1
> -		 */
> -		e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
> -		phy_data |= CV_SMB_CTRL_FORCE_SMBUS;
> -		e1e_wphy(hw, CV_SMB_CTRL, phy_data);
> -		mac_data = er32(CTRL_EXT);
> -		mac_data |= E1000_CTRL_EXT_FORCE_SMBUS;
> -		ew32(CTRL_EXT, mac_data);
> -
> -		/* DFT control: PHY bit: page769_20[0] = 1
> -		 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1
> -		 */
> -		e1e_rphy(hw, I82579_DFT_CTRL, &phy_data);
> -		phy_data |= BIT(0);
> -		e1e_wphy(hw, I82579_DFT_CTRL, phy_data);
> -
> -		mac_data = er32(EXTCNF_CTRL);
> -		mac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
> -		ew32(EXTCNF_CTRL, mac_data);
> -
> -		/* Enable the Dynamic Power Gating in the MAC */
> -		mac_data = er32(FEXTNVM7);
> -		mac_data |= BIT(22);
> -		ew32(FEXTNVM7, mac_data);
> -
> -		/* Disable disconnected cable conditioning for Power Gating */
> -		mac_data = er32(DPGFR);
> -		mac_data |= BIT(2);
> -		ew32(DPGFR, mac_data);
> -
> -		/* Don't wake from dynamic Power Gating with clock request */
> -		mac_data = er32(FEXTNVM12);
> -		mac_data |= BIT(12);
> -		ew32(FEXTNVM12, mac_data);
> -
> -		/* Ungate PGCB clock */
> -		mac_data = er32(FEXTNVM9);
> -		mac_data &= ~BIT(28);
> -		ew32(FEXTNVM9, mac_data);
> -
> -		/* Enable K1 off to enable mPHY Power Gating */
> -		mac_data = er32(FEXTNVM6);
> -		mac_data |= BIT(31);
> -		ew32(FEXTNVM6, mac_data);
> -
> -		/* Enable mPHY power gating for any link and speed */
> -		mac_data = er32(FEXTNVM8);
> -		mac_data |= BIT(9);
> -		ew32(FEXTNVM8, mac_data);
> -
> -		/* Enable the Dynamic Clock Gating in the DMA and MAC */
> -		mac_data = er32(CTRL_EXT);
> -		mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN;
> -		ew32(CTRL_EXT, mac_data);
> -
> -		/* No MAC DPG gating SLP_S0 in modern standby
> -		 * Switch the logic of the lanphypc to use PMC counter
> -		 */
> -		mac_data = er32(FEXTNVM5);
> -		mac_data |= BIT(7);
> -		ew32(FEXTNVM5, mac_data);
> -	}
> +	/* Disable the periodic inband message,
> +	 * don't request PCIe clock in K1 page770_17[10:9] = 10b
> +	 */
> +	e1e_rphy(hw, HV_PM_CTRL, &phy_data);
> +	phy_data &= ~HV_PM_CTRL_K1_CLK_REQ;
> +	phy_data |= BIT(10);
> +	e1e_wphy(hw, HV_PM_CTRL, phy_data);
>   
> -	/* Disable the time synchronization clock */
> -	mac_data = er32(FEXTNVM7);
> -	mac_data |= BIT(31);
> -	mac_data &= ~BIT(0);
> -	ew32(FEXTNVM7, mac_data);
> +	/* Make sure we don't exit K1 every time a new packet arrives
> +	 * 772_29[5] = 1 CS_Mode_Stay_In_K1
> +	 */
> +	e1e_rphy(hw, I217_CGFREG, &phy_data);
> +	phy_data |= BIT(5);
> +	e1e_wphy(hw, I217_CGFREG, phy_data);
>   
> -	/* Dynamic Power Gating Enable */
> +	/* Change the MAC/PHY interface to SMBus
> +	 * Force the SMBus in PHY page769_23[0] = 1
> +	 * Force the SMBus in MAC CTRL_EXT[11] = 1
> +	 */
> +	e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
> +	phy_data |= CV_SMB_CTRL_FORCE_SMBUS;
> +	e1e_wphy(hw, CV_SMB_CTRL, phy_data);
>   	mac_data = er32(CTRL_EXT);
> -	mac_data |= BIT(3);
> +	mac_data |= E1000_CTRL_EXT_FORCE_SMBUS;
>   	ew32(CTRL_EXT, mac_data);
>   
> +	/* DFT control: PHY bit: page769_20[0] = 1
> +	 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1
> +	 */
> +	e1e_rphy(hw, I82579_DFT_CTRL, &phy_data);
> +	phy_data |= BIT(0);
> +	e1e_wphy(hw, I82579_DFT_CTRL, phy_data);
> +
> +	mac_data = er32(EXTCNF_CTRL);
> +	mac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
> +	ew32(EXTCNF_CTRL, mac_data);
> +
>   	/* Check MAC Tx/Rx packet buffer pointers.
>   	 * Reset MAC Tx/Rx packet buffer pointers to suppress any
>   	 * pending traffic indication that would prevent power gating.
> @@ -6478,6 +6416,59 @@ static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter)
>   	mac_data = er32(RDFPC);
>   	if (mac_data)
>   		ew32(RDFPC, 0);
> +
> +	/* Enable the Dynamic Power Gating in the MAC */
> +	mac_data = er32(FEXTNVM7);
> +	mac_data |= BIT(22);
> +	ew32(FEXTNVM7, mac_data);
> +
> +	/* Disable the time synchronization clock */
> +	mac_data = er32(FEXTNVM7);
> +	mac_data |= BIT(31);
> +	mac_data &= ~BIT(0);
> +	ew32(FEXTNVM7, mac_data);
> +
> +	/* Dynamic Power Gating Enable */
> +	mac_data = er32(CTRL_EXT);
> +	mac_data |= BIT(3);
> +	ew32(CTRL_EXT, mac_data);
> +
> +	/* Disable disconnected cable conditioning for Power Gating */
> +	mac_data = er32(DPGFR);
> +	mac_data |= BIT(2);
> +	ew32(DPGFR, mac_data);
> +
> +	/* Don't wake from dynamic Power Gating with clock request */
> +	mac_data = er32(FEXTNVM12);
> +	mac_data |= BIT(12);
> +	ew32(FEXTNVM12, mac_data);
> +
> +	/* Ungate PGCB clock */
> +	mac_data = er32(FEXTNVM9);
> +	mac_data &= ~BIT(28);
> +	ew32(FEXTNVM9, mac_data);
> +
> +	/* Enable K1 off to enable mPHY Power Gating */
> +	mac_data = er32(FEXTNVM6);
> +	mac_data |= BIT(31);
> +	ew32(FEXTNVM6, mac_data);
> +
> +	/* Enable mPHY power gating for any link and speed */
> +	mac_data = er32(FEXTNVM8);
> +	mac_data |= BIT(9);
> +	ew32(FEXTNVM8, mac_data);
> +
> +	/* Enable the Dynamic Clock Gating in the DMA and MAC */
> +	mac_data = er32(CTRL_EXT);
> +	mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN;
> +	ew32(CTRL_EXT, mac_data);
> +
> +	/* No MAC DPG gating SLP_S0 in modern standby
> +	 * Switch the logic of the lanphypc to use PMC counter
> +	 */
> +	mac_data = er32(FEXTNVM5);
> +	mac_data |= BIT(7);
> +	ew32(FEXTNVM5, mac_data);
>   }
>   
>   static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter)
> @@ -6486,98 +6477,87 @@ static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter)
>   	u32 mac_data;
>   	u16 phy_data;
>   
> -	if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
> -		/* Request ME unconfigure the device from S0ix */
> -		mac_data = er32(H2ME);
> -		mac_data &= ~E1000_H2ME_START_DPG;
> -		mac_data |= E1000_H2ME_EXIT_DPG;
> -		ew32(H2ME, mac_data);
> -	} else {
> -		/* Request driver unconfigure the device from S0ix */
> -
> -		/* Disable the Dynamic Power Gating in the MAC */
> -		mac_data = er32(FEXTNVM7);
> -		mac_data &= 0xFFBFFFFF;
> -		ew32(FEXTNVM7, mac_data);
> -
> -		/* Disable mPHY power gating for any link and speed */
> -		mac_data = er32(FEXTNVM8);
> -		mac_data &= ~BIT(9);
> -		ew32(FEXTNVM8, mac_data);
> -
> -		/* Disable K1 off */
> -		mac_data = er32(FEXTNVM6);
> -		mac_data &= ~BIT(31);
> -		ew32(FEXTNVM6, mac_data);
> -
> -		/* Disable Ungate PGCB clock */
> -		mac_data = er32(FEXTNVM9);
> -		mac_data |= BIT(28);
> -		ew32(FEXTNVM9, mac_data);
> -
> -		/* Cancel not waking from dynamic
> -		 * Power Gating with clock request
> -		 */
> -		mac_data = er32(FEXTNVM12);
> -		mac_data &= ~BIT(12);
> -		ew32(FEXTNVM12, mac_data);
> +	/* Disable the Dynamic Power Gating in the MAC */
> +	mac_data = er32(FEXTNVM7);
> +	mac_data &= 0xFFBFFFFF;
> +	ew32(FEXTNVM7, mac_data);
>   
> -		/* Cancel disable disconnected cable conditioning
> -		 * for Power Gating
> -		 */
> -		mac_data = er32(DPGFR);
> -		mac_data &= ~BIT(2);
> -		ew32(DPGFR, mac_data);
> +	/* Enable the time synchronization clock */
> +	mac_data = er32(FEXTNVM7);
> +	mac_data |= BIT(0);
> +	ew32(FEXTNVM7, mac_data);
>   
> -		/* Disable the Dynamic Clock Gating in the DMA and MAC */
> -		mac_data = er32(CTRL_EXT);
> -		mac_data &= 0xFFF7FFFF;
> -		ew32(CTRL_EXT, mac_data);
> +	/* Disable mPHY power gating for any link and speed */
> +	mac_data = er32(FEXTNVM8);
> +	mac_data &= ~BIT(9);
> +	ew32(FEXTNVM8, mac_data);
>   
> -		/* Revert the lanphypc logic to use the internal Gbe counter
> -		 * and not the PMC counter
> -		 */
> -		mac_data = er32(FEXTNVM5);
> -		mac_data &= 0xFFFFFF7F;
> -		ew32(FEXTNVM5, mac_data);
> +	/* Disable K1 off */
> +	mac_data = er32(FEXTNVM6);
> +	mac_data &= ~BIT(31);
> +	ew32(FEXTNVM6, mac_data);
>   
> -		/* Enable the periodic inband message,
> -		 * Request PCIe clock in K1 page770_17[10:9] =01b
> -		 */
> -		e1e_rphy(hw, HV_PM_CTRL, &phy_data);
> -		phy_data &= 0xFBFF;
> -		phy_data |= HV_PM_CTRL_K1_CLK_REQ;
> -		e1e_wphy(hw, HV_PM_CTRL, phy_data);
> +	/* Disable Ungate PGCB clock */
> +	mac_data = er32(FEXTNVM9);
> +	mac_data |= BIT(28);
> +	ew32(FEXTNVM9, mac_data);
>   
> -		/* Return back configuration
> -		 * 772_29[5] = 0 CS_Mode_Stay_In_K1
> -		 */
> -		e1e_rphy(hw, I217_CGFREG, &phy_data);
> -		phy_data &= 0xFFDF;
> -		e1e_wphy(hw, I217_CGFREG, phy_data);
> +	/* Cancel not waking from dynamic
> +	 * Power Gating with clock request
> +	 */
> +	mac_data = er32(FEXTNVM12);
> +	mac_data &= ~BIT(12);
> +	ew32(FEXTNVM12, mac_data);
>   
> -		/* Change the MAC/PHY interface to Kumeran
> -		 * Unforce the SMBus in PHY page769_23[0] = 0
> -		 * Unforce the SMBus in MAC CTRL_EXT[11] = 0
> -		 */
> -		e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
> -		phy_data &= ~CV_SMB_CTRL_FORCE_SMBUS;
> -		e1e_wphy(hw, CV_SMB_CTRL, phy_data);
> -		mac_data = er32(CTRL_EXT);
> -		mac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS;
> -		ew32(CTRL_EXT, mac_data);
> -	}
> +	/* Cancel disable disconnected cable conditioning
> +	 * for Power Gating
> +	 */
> +	mac_data = er32(DPGFR);
> +	mac_data &= ~BIT(2);
> +	ew32(DPGFR, mac_data);
>   
>   	/* Disable Dynamic Power Gating */
>   	mac_data = er32(CTRL_EXT);
>   	mac_data &= 0xFFFFFFF7;
>   	ew32(CTRL_EXT, mac_data);
>   
> -	/* Enable the time synchronization clock */
> -	mac_data = er32(FEXTNVM7);
> -	mac_data &= ~BIT(31);
> -	mac_data |= BIT(0);
> -	ew32(FEXTNVM7, mac_data);
> +	/* Disable the Dynamic Clock Gating in the DMA and MAC */
> +	mac_data = er32(CTRL_EXT);
> +	mac_data &= 0xFFF7FFFF;
> +	ew32(CTRL_EXT, mac_data);
> +
> +	/* Revert the lanphypc logic to use the internal Gbe counter
> +	 * and not the PMC counter
> +	 */
> +	mac_data = er32(FEXTNVM5);
> +	mac_data &= 0xFFFFFF7F;
> +	ew32(FEXTNVM5, mac_data);
> +
> +	/* Enable the periodic inband message,
> +	 * Request PCIe clock in K1 page770_17[10:9] =01b
> +	 */
> +	e1e_rphy(hw, HV_PM_CTRL, &phy_data);
> +	phy_data &= 0xFBFF;
> +	phy_data |= HV_PM_CTRL_K1_CLK_REQ;
> +	e1e_wphy(hw, HV_PM_CTRL, phy_data);
> +
> +	/* Return back configuration
> +	 * 772_29[5] = 0 CS_Mode_Stay_In_K1
> +	 */
> +	e1e_rphy(hw, I217_CGFREG, &phy_data);
> +	phy_data &= 0xFFDF;
> +	e1e_wphy(hw, I217_CGFREG, phy_data);
> +
> +	/* Change the MAC/PHY interface to Kumeran
> +	 * Unforce the SMBus in PHY page769_23[0] = 0
> +	 * Unforce the SMBus in MAC CTRL_EXT[11] = 0
> +	 */
> +	e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
> +	phy_data &= ~CV_SMB_CTRL_FORCE_SMBUS;
> +	e1e_wphy(hw, CV_SMB_CTRL, phy_data);
> +	mac_data = er32(CTRL_EXT);
> +	mac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS;
> +	ew32(CTRL_EXT, mac_data);
>   }
>   
>   static int e1000e_pm_freeze(struct device *dev)
> 
Hello Kai-Heng,
I believe it is the wrong approach. Reverting this patch will put 
corporate systems in an unpredictable state. SW will perform s0ix flow 
independent to CSME. (The CSME firmware will continue run 
independently.) LAN controller could be in an unknown state.
Please, afford us to continue to debug the problem (it is could be 
incredible complexity)

You always can skip the s0ix flow on problematic corporate systems by 
using privilege flag: ethtool --set-priv-flags enp0s31f6 s0ix-enabled off

Also, there is no impact on consumer systems.
Sasha
Mark Pearson Nov. 30, 2021, 3:52 p.m. UTC | #2
Hi Sasha

On 2021-11-28 08:23, Sasha Neftin wrote:
> On 11/22/2021 18:19, Kai-Heng Feng wrote:
>> This reverts commit 3e55d231716ea361b1520b801c6778c4c48de102.
>>
>> Bugzilla:
>> https://bugzilla.kernel.org/show_bug.cgi?id=214821>>>
>> Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
>> ---
<snip>
>>
> Hello Kai-Heng,
> I believe it is the wrong approach. Reverting this patch will put
> corporate systems in an unpredictable state. SW will perform s0ix flow
> independent to CSME. (The CSME firmware will continue run
> independently.) LAN controller could be in an unknown state.
> Please, afford us to continue to debug the problem (it is could be
> incredible complexity)
> 
> You always can skip the s0ix flow on problematic corporate systems by
> using privilege flag: ethtool --set-priv-flags enp0s31f6 s0ix-enabled off
> 
> Also, there is no impact on consumer systems.
> Sasha

I know we've discussed this offline, and your team are working on the
correct fix but I wanted to check based on your comments above that "it
was complex". I thought, and maybe misunderstood, that it was going to
be relatively simple to disable the change for older CPUs - which is the
biggest problem caused by the patch.

Right now it's breaking networking for folk who happen to have a vPro
Tigerlake (and I believe even potentially Cometlake or older) system. I
think the impact of that could potentially be quite severe.

I understand not wanting to revert the change for the ADL platforms I
believe this is targeting and to fix this instead - but your comment
made me nervous that Linux users on older Intel based platforms are in
for a long and painful wait - it is likely a lot of users....

Can you or Dima confirm the fix for older platforms will be available
soon? I appreciate the ADL platform might take a bit more work and time
to get right.

Thanks
Mark
Ruinskiy, Dima Dec. 1, 2021, 4:38 p.m. UTC | #3
On 30/11/2021 17:52, Mark Pearson wrote:
> Hi Sasha
> 
> On 2021-11-28 08:23, Sasha Neftin wrote:
>> On 11/22/2021 18:19, Kai-Heng Feng wrote:
>>> This reverts commit 3e55d231716ea361b1520b801c6778c4c48de102.
>>>
>>> Bugzilla:
>>> https://bugzilla.kernel.org/show_bug.cgi?id=214821>>>
>>> Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
>>> ---
> <snip>
>>>
>> Hello Kai-Heng,
>> I believe it is the wrong approach. Reverting this patch will put
>> corporate systems in an unpredictable state. SW will perform s0ix flow
>> independent to CSME. (The CSME firmware will continue run
>> independently.) LAN controller could be in an unknown state.
>> Please, afford us to continue to debug the problem (it is could be
>> incredible complexity)
>>
>> You always can skip the s0ix flow on problematic corporate systems by
>> using privilege flag: ethtool --set-priv-flags enp0s31f6 s0ix-enabled off
>>
>> Also, there is no impact on consumer systems.
>> Sasha
> 
> I know we've discussed this offline, and your team are working on the
> correct fix but I wanted to check based on your comments above that "it
> was complex". I thought, and maybe misunderstood, that it was going to
> be relatively simple to disable the change for older CPUs - which is the
> biggest problem caused by the patch.
> 
> Right now it's breaking networking for folk who happen to have a vPro
> Tigerlake (and I believe even potentially Cometlake or older) system. I
> think the impact of that could potentially be quite severe.
> 
> I understand not wanting to revert the change for the ADL platforms I
> believe this is targeting and to fix this instead - but your comment
> made me nervous that Linux users on older Intel based platforms are in
> for a long and painful wait - it is likely a lot of users....
> 
> Can you or Dima confirm the fix for older platforms will be available
> soon? I appreciate the ADL platform might take a bit more work and time
> to get right.
> 
> Thanks
> Mark
> 
Hi Mark,

What we currently see is that the issue manifests itself similarly on 
ADL and TGL platforms. Thus, the fix will likely be the same for both.

If we cannot find a proper fix soon, we will provide a workaround (for 
example by temporary disabling the feature on vPro platforms until we do 
have a fix).

This can be done without reverting the patch series, and I don't see 
much value in selectively disabling it for CML/TGL while leaving it on 
for ADL, unless our ongoing debug shows otherwise.

--Dima
Mark Pearson Dec. 1, 2021, 7 p.m. UTC | #4
On 2021-12-01 11:38, Ruinskiy, Dima wrote:
> On 30/11/2021 17:52, Mark Pearson wrote:
>> Hi Sasha
>>
>> On 2021-11-28 08:23, Sasha Neftin wrote:
>>> On 11/22/2021 18:19, Kai-Heng Feng wrote:
>>>> This reverts commit 3e55d231716ea361b1520b801c6778c4c48de102.
>>>>
>>>> Bugzilla:
>>>> https://bugzilla.kernel.org/show_bug.cgi?id=214821>>>>>
>>>> Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
>>>> ---
>> <snip>
>>>>
>>> Hello Kai-Heng,
>>> I believe it is the wrong approach. Reverting this patch will put
>>> corporate systems in an unpredictable state. SW will perform s0ix flow
>>> independent to CSME. (The CSME firmware will continue run
>>> independently.) LAN controller could be in an unknown state.
>>> Please, afford us to continue to debug the problem (it is could be
>>> incredible complexity)
>>>
>>> You always can skip the s0ix flow on problematic corporate systems by
>>> using privilege flag: ethtool --set-priv-flags enp0s31f6 s0ix-enabled
>>> off
>>>
>>> Also, there is no impact on consumer systems.
>>> Sasha
>>
>> I know we've discussed this offline, and your team are working on the
>> correct fix but I wanted to check based on your comments above that "it
>> was complex". I thought, and maybe misunderstood, that it was going to
>> be relatively simple to disable the change for older CPUs - which is the
>> biggest problem caused by the patch.
>>
>> Right now it's breaking networking for folk who happen to have a vPro
>> Tigerlake (and I believe even potentially Cometlake or older) system. I
>> think the impact of that could potentially be quite severe.
>>
>> I understand not wanting to revert the change for the ADL platforms I
>> believe this is targeting and to fix this instead - but your comment
>> made me nervous that Linux users on older Intel based platforms are in
>> for a long and painful wait - it is likely a lot of users....
>>
>> Can you or Dima confirm the fix for older platforms will be available
>> soon? I appreciate the ADL platform might take a bit more work and time
>> to get right.
>>
>> Thanks
>> Mark
>>
> Hi Mark,
> 
> What we currently see is that the issue manifests itself similarly on
> ADL and TGL platforms. Thus, the fix will likely be the same for both.
> 
> If we cannot find a proper fix soon, we will provide a workaround (for
> example by temporary disabling the feature on vPro platforms until we do
> have a fix).
> 
> This can be done without reverting the patch series, and I don't see
> much value in selectively disabling it for CML/TGL while leaving it on
> for ADL, unless our ongoing debug shows otherwise.
> 
Got it - thanks Dima.

As a note - the obvious advantage of selectively disabling for CML/TGL
is there is a ton of those platforms out there in users hands, whereas
the ADL platforms won't be landing for a few more months (at least in
our case). I'm OK if the fixes take a touch longer with ADL (though
we'll want them soon so they have time to make it upstream and down into
the distro's) - but there's going to be a lot of unhappy Intel users as
soon as they start picking up the updates (that are landing in some
distro's) and finding that networking is broken. I'd expect TGL/CML to
be a priority...

Keep us posted when the fix is ready please.

Mark
diff mbox series

Patch

diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.h b/drivers/net/ethernet/intel/e1000e/ich8lan.h
index 1dfa1d28dae64..8f2a8f4ce0ee4 100644
--- a/drivers/net/ethernet/intel/e1000e/ich8lan.h
+++ b/drivers/net/ethernet/intel/e1000e/ich8lan.h
@@ -47,8 +47,6 @@ 
 #define E1000_SHRAH_PCH_LPT(_i)		(0x0540C + ((_i) * 8))
 
 #define E1000_H2ME		0x05B50	/* Host to ME */
-#define E1000_H2ME_START_DPG	0x00000001	/* indicate the ME of DPG */
-#define E1000_H2ME_EXIT_DPG	0x00000002	/* indicate the ME exit DPG */
 #define E1000_H2ME_ULP		0x00000800	/* ULP Indication Bit */
 #define E1000_H2ME_ENFORCE_SETTINGS	0x00001000	/* Enforce Settings */
 
diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c
index 242314809e59c..52c91c52b971b 100644
--- a/drivers/net/ethernet/intel/e1000e/netdev.c
+++ b/drivers/net/ethernet/intel/e1000e/netdev.c
@@ -6345,105 +6345,43 @@  static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter)
 	u32 mac_data;
 	u16 phy_data;
 
-	if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
-		/* Request ME configure the device for S0ix */
-		mac_data = er32(H2ME);
-		mac_data |= E1000_H2ME_START_DPG;
-		mac_data &= ~E1000_H2ME_EXIT_DPG;
-		ew32(H2ME, mac_data);
-	} else {
-		/* Request driver configure the device to S0ix */
-		/* Disable the periodic inband message,
-		 * don't request PCIe clock in K1 page770_17[10:9] = 10b
-		 */
-		e1e_rphy(hw, HV_PM_CTRL, &phy_data);
-		phy_data &= ~HV_PM_CTRL_K1_CLK_REQ;
-		phy_data |= BIT(10);
-		e1e_wphy(hw, HV_PM_CTRL, phy_data);
-
-		/* Make sure we don't exit K1 every time a new packet arrives
-		 * 772_29[5] = 1 CS_Mode_Stay_In_K1
-		 */
-		e1e_rphy(hw, I217_CGFREG, &phy_data);
-		phy_data |= BIT(5);
-		e1e_wphy(hw, I217_CGFREG, phy_data);
-
-		/* Change the MAC/PHY interface to SMBus
-		 * Force the SMBus in PHY page769_23[0] = 1
-		 * Force the SMBus in MAC CTRL_EXT[11] = 1
-		 */
-		e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
-		phy_data |= CV_SMB_CTRL_FORCE_SMBUS;
-		e1e_wphy(hw, CV_SMB_CTRL, phy_data);
-		mac_data = er32(CTRL_EXT);
-		mac_data |= E1000_CTRL_EXT_FORCE_SMBUS;
-		ew32(CTRL_EXT, mac_data);
-
-		/* DFT control: PHY bit: page769_20[0] = 1
-		 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1
-		 */
-		e1e_rphy(hw, I82579_DFT_CTRL, &phy_data);
-		phy_data |= BIT(0);
-		e1e_wphy(hw, I82579_DFT_CTRL, phy_data);
-
-		mac_data = er32(EXTCNF_CTRL);
-		mac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
-		ew32(EXTCNF_CTRL, mac_data);
-
-		/* Enable the Dynamic Power Gating in the MAC */
-		mac_data = er32(FEXTNVM7);
-		mac_data |= BIT(22);
-		ew32(FEXTNVM7, mac_data);
-
-		/* Disable disconnected cable conditioning for Power Gating */
-		mac_data = er32(DPGFR);
-		mac_data |= BIT(2);
-		ew32(DPGFR, mac_data);
-
-		/* Don't wake from dynamic Power Gating with clock request */
-		mac_data = er32(FEXTNVM12);
-		mac_data |= BIT(12);
-		ew32(FEXTNVM12, mac_data);
-
-		/* Ungate PGCB clock */
-		mac_data = er32(FEXTNVM9);
-		mac_data &= ~BIT(28);
-		ew32(FEXTNVM9, mac_data);
-
-		/* Enable K1 off to enable mPHY Power Gating */
-		mac_data = er32(FEXTNVM6);
-		mac_data |= BIT(31);
-		ew32(FEXTNVM6, mac_data);
-
-		/* Enable mPHY power gating for any link and speed */
-		mac_data = er32(FEXTNVM8);
-		mac_data |= BIT(9);
-		ew32(FEXTNVM8, mac_data);
-
-		/* Enable the Dynamic Clock Gating in the DMA and MAC */
-		mac_data = er32(CTRL_EXT);
-		mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN;
-		ew32(CTRL_EXT, mac_data);
-
-		/* No MAC DPG gating SLP_S0 in modern standby
-		 * Switch the logic of the lanphypc to use PMC counter
-		 */
-		mac_data = er32(FEXTNVM5);
-		mac_data |= BIT(7);
-		ew32(FEXTNVM5, mac_data);
-	}
+	/* Disable the periodic inband message,
+	 * don't request PCIe clock in K1 page770_17[10:9] = 10b
+	 */
+	e1e_rphy(hw, HV_PM_CTRL, &phy_data);
+	phy_data &= ~HV_PM_CTRL_K1_CLK_REQ;
+	phy_data |= BIT(10);
+	e1e_wphy(hw, HV_PM_CTRL, phy_data);
 
-	/* Disable the time synchronization clock */
-	mac_data = er32(FEXTNVM7);
-	mac_data |= BIT(31);
-	mac_data &= ~BIT(0);
-	ew32(FEXTNVM7, mac_data);
+	/* Make sure we don't exit K1 every time a new packet arrives
+	 * 772_29[5] = 1 CS_Mode_Stay_In_K1
+	 */
+	e1e_rphy(hw, I217_CGFREG, &phy_data);
+	phy_data |= BIT(5);
+	e1e_wphy(hw, I217_CGFREG, phy_data);
 
-	/* Dynamic Power Gating Enable */
+	/* Change the MAC/PHY interface to SMBus
+	 * Force the SMBus in PHY page769_23[0] = 1
+	 * Force the SMBus in MAC CTRL_EXT[11] = 1
+	 */
+	e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
+	phy_data |= CV_SMB_CTRL_FORCE_SMBUS;
+	e1e_wphy(hw, CV_SMB_CTRL, phy_data);
 	mac_data = er32(CTRL_EXT);
-	mac_data |= BIT(3);
+	mac_data |= E1000_CTRL_EXT_FORCE_SMBUS;
 	ew32(CTRL_EXT, mac_data);
 
+	/* DFT control: PHY bit: page769_20[0] = 1
+	 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1
+	 */
+	e1e_rphy(hw, I82579_DFT_CTRL, &phy_data);
+	phy_data |= BIT(0);
+	e1e_wphy(hw, I82579_DFT_CTRL, phy_data);
+
+	mac_data = er32(EXTCNF_CTRL);
+	mac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
+	ew32(EXTCNF_CTRL, mac_data);
+
 	/* Check MAC Tx/Rx packet buffer pointers.
 	 * Reset MAC Tx/Rx packet buffer pointers to suppress any
 	 * pending traffic indication that would prevent power gating.
@@ -6478,6 +6416,59 @@  static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter)
 	mac_data = er32(RDFPC);
 	if (mac_data)
 		ew32(RDFPC, 0);
+
+	/* Enable the Dynamic Power Gating in the MAC */
+	mac_data = er32(FEXTNVM7);
+	mac_data |= BIT(22);
+	ew32(FEXTNVM7, mac_data);
+
+	/* Disable the time synchronization clock */
+	mac_data = er32(FEXTNVM7);
+	mac_data |= BIT(31);
+	mac_data &= ~BIT(0);
+	ew32(FEXTNVM7, mac_data);
+
+	/* Dynamic Power Gating Enable */
+	mac_data = er32(CTRL_EXT);
+	mac_data |= BIT(3);
+	ew32(CTRL_EXT, mac_data);
+
+	/* Disable disconnected cable conditioning for Power Gating */
+	mac_data = er32(DPGFR);
+	mac_data |= BIT(2);
+	ew32(DPGFR, mac_data);
+
+	/* Don't wake from dynamic Power Gating with clock request */
+	mac_data = er32(FEXTNVM12);
+	mac_data |= BIT(12);
+	ew32(FEXTNVM12, mac_data);
+
+	/* Ungate PGCB clock */
+	mac_data = er32(FEXTNVM9);
+	mac_data &= ~BIT(28);
+	ew32(FEXTNVM9, mac_data);
+
+	/* Enable K1 off to enable mPHY Power Gating */
+	mac_data = er32(FEXTNVM6);
+	mac_data |= BIT(31);
+	ew32(FEXTNVM6, mac_data);
+
+	/* Enable mPHY power gating for any link and speed */
+	mac_data = er32(FEXTNVM8);
+	mac_data |= BIT(9);
+	ew32(FEXTNVM8, mac_data);
+
+	/* Enable the Dynamic Clock Gating in the DMA and MAC */
+	mac_data = er32(CTRL_EXT);
+	mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN;
+	ew32(CTRL_EXT, mac_data);
+
+	/* No MAC DPG gating SLP_S0 in modern standby
+	 * Switch the logic of the lanphypc to use PMC counter
+	 */
+	mac_data = er32(FEXTNVM5);
+	mac_data |= BIT(7);
+	ew32(FEXTNVM5, mac_data);
 }
 
 static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter)
@@ -6486,98 +6477,87 @@  static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter)
 	u32 mac_data;
 	u16 phy_data;
 
-	if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
-		/* Request ME unconfigure the device from S0ix */
-		mac_data = er32(H2ME);
-		mac_data &= ~E1000_H2ME_START_DPG;
-		mac_data |= E1000_H2ME_EXIT_DPG;
-		ew32(H2ME, mac_data);
-	} else {
-		/* Request driver unconfigure the device from S0ix */
-
-		/* Disable the Dynamic Power Gating in the MAC */
-		mac_data = er32(FEXTNVM7);
-		mac_data &= 0xFFBFFFFF;
-		ew32(FEXTNVM7, mac_data);
-
-		/* Disable mPHY power gating for any link and speed */
-		mac_data = er32(FEXTNVM8);
-		mac_data &= ~BIT(9);
-		ew32(FEXTNVM8, mac_data);
-
-		/* Disable K1 off */
-		mac_data = er32(FEXTNVM6);
-		mac_data &= ~BIT(31);
-		ew32(FEXTNVM6, mac_data);
-
-		/* Disable Ungate PGCB clock */
-		mac_data = er32(FEXTNVM9);
-		mac_data |= BIT(28);
-		ew32(FEXTNVM9, mac_data);
-
-		/* Cancel not waking from dynamic
-		 * Power Gating with clock request
-		 */
-		mac_data = er32(FEXTNVM12);
-		mac_data &= ~BIT(12);
-		ew32(FEXTNVM12, mac_data);
+	/* Disable the Dynamic Power Gating in the MAC */
+	mac_data = er32(FEXTNVM7);
+	mac_data &= 0xFFBFFFFF;
+	ew32(FEXTNVM7, mac_data);
 
-		/* Cancel disable disconnected cable conditioning
-		 * for Power Gating
-		 */
-		mac_data = er32(DPGFR);
-		mac_data &= ~BIT(2);
-		ew32(DPGFR, mac_data);
+	/* Enable the time synchronization clock */
+	mac_data = er32(FEXTNVM7);
+	mac_data |= BIT(0);
+	ew32(FEXTNVM7, mac_data);
 
-		/* Disable the Dynamic Clock Gating in the DMA and MAC */
-		mac_data = er32(CTRL_EXT);
-		mac_data &= 0xFFF7FFFF;
-		ew32(CTRL_EXT, mac_data);
+	/* Disable mPHY power gating for any link and speed */
+	mac_data = er32(FEXTNVM8);
+	mac_data &= ~BIT(9);
+	ew32(FEXTNVM8, mac_data);
 
-		/* Revert the lanphypc logic to use the internal Gbe counter
-		 * and not the PMC counter
-		 */
-		mac_data = er32(FEXTNVM5);
-		mac_data &= 0xFFFFFF7F;
-		ew32(FEXTNVM5, mac_data);
+	/* Disable K1 off */
+	mac_data = er32(FEXTNVM6);
+	mac_data &= ~BIT(31);
+	ew32(FEXTNVM6, mac_data);
 
-		/* Enable the periodic inband message,
-		 * Request PCIe clock in K1 page770_17[10:9] =01b
-		 */
-		e1e_rphy(hw, HV_PM_CTRL, &phy_data);
-		phy_data &= 0xFBFF;
-		phy_data |= HV_PM_CTRL_K1_CLK_REQ;
-		e1e_wphy(hw, HV_PM_CTRL, phy_data);
+	/* Disable Ungate PGCB clock */
+	mac_data = er32(FEXTNVM9);
+	mac_data |= BIT(28);
+	ew32(FEXTNVM9, mac_data);
 
-		/* Return back configuration
-		 * 772_29[5] = 0 CS_Mode_Stay_In_K1
-		 */
-		e1e_rphy(hw, I217_CGFREG, &phy_data);
-		phy_data &= 0xFFDF;
-		e1e_wphy(hw, I217_CGFREG, phy_data);
+	/* Cancel not waking from dynamic
+	 * Power Gating with clock request
+	 */
+	mac_data = er32(FEXTNVM12);
+	mac_data &= ~BIT(12);
+	ew32(FEXTNVM12, mac_data);
 
-		/* Change the MAC/PHY interface to Kumeran
-		 * Unforce the SMBus in PHY page769_23[0] = 0
-		 * Unforce the SMBus in MAC CTRL_EXT[11] = 0
-		 */
-		e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
-		phy_data &= ~CV_SMB_CTRL_FORCE_SMBUS;
-		e1e_wphy(hw, CV_SMB_CTRL, phy_data);
-		mac_data = er32(CTRL_EXT);
-		mac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS;
-		ew32(CTRL_EXT, mac_data);
-	}
+	/* Cancel disable disconnected cable conditioning
+	 * for Power Gating
+	 */
+	mac_data = er32(DPGFR);
+	mac_data &= ~BIT(2);
+	ew32(DPGFR, mac_data);
 
 	/* Disable Dynamic Power Gating */
 	mac_data = er32(CTRL_EXT);
 	mac_data &= 0xFFFFFFF7;
 	ew32(CTRL_EXT, mac_data);
 
-	/* Enable the time synchronization clock */
-	mac_data = er32(FEXTNVM7);
-	mac_data &= ~BIT(31);
-	mac_data |= BIT(0);
-	ew32(FEXTNVM7, mac_data);
+	/* Disable the Dynamic Clock Gating in the DMA and MAC */
+	mac_data = er32(CTRL_EXT);
+	mac_data &= 0xFFF7FFFF;
+	ew32(CTRL_EXT, mac_data);
+
+	/* Revert the lanphypc logic to use the internal Gbe counter
+	 * and not the PMC counter
+	 */
+	mac_data = er32(FEXTNVM5);
+	mac_data &= 0xFFFFFF7F;
+	ew32(FEXTNVM5, mac_data);
+
+	/* Enable the periodic inband message,
+	 * Request PCIe clock in K1 page770_17[10:9] =01b
+	 */
+	e1e_rphy(hw, HV_PM_CTRL, &phy_data);
+	phy_data &= 0xFBFF;
+	phy_data |= HV_PM_CTRL_K1_CLK_REQ;
+	e1e_wphy(hw, HV_PM_CTRL, phy_data);
+
+	/* Return back configuration
+	 * 772_29[5] = 0 CS_Mode_Stay_In_K1
+	 */
+	e1e_rphy(hw, I217_CGFREG, &phy_data);
+	phy_data &= 0xFFDF;
+	e1e_wphy(hw, I217_CGFREG, phy_data);
+
+	/* Change the MAC/PHY interface to Kumeran
+	 * Unforce the SMBus in PHY page769_23[0] = 0
+	 * Unforce the SMBus in MAC CTRL_EXT[11] = 0
+	 */
+	e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
+	phy_data &= ~CV_SMB_CTRL_FORCE_SMBUS;
+	e1e_wphy(hw, CV_SMB_CTRL, phy_data);
+	mac_data = er32(CTRL_EXT);
+	mac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS;
+	ew32(CTRL_EXT, mac_data);
 }
 
 static int e1000e_pm_freeze(struct device *dev)