From patchwork Fri Mar 10 20:22:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Pujari, Bimmy" X-Patchwork-Id: 737546 X-Patchwork-Delegate: jeffrey.t.kirsher@intel.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vfxys0lgFz9s7k for ; Sat, 11 Mar 2017 06:24:21 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id 553D289CE5; Fri, 10 Mar 2017 19:24:19 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Axnz+UlkUZcR; Fri, 10 Mar 2017 19:24:17 +0000 (UTC) Received: from ash.osuosl.org (ash.osuosl.org [140.211.166.34]) by whitealder.osuosl.org (Postfix) with ESMTP id 8690489CC3; Fri, 10 Mar 2017 19:24:17 +0000 (UTC) X-Original-To: intel-wired-lan@lists.osuosl.org Delivered-To: intel-wired-lan@lists.osuosl.org Received: from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138]) by ash.osuosl.org (Postfix) with ESMTP id F35B31C0169 for ; Fri, 10 Mar 2017 19:24:15 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id EF89E89CEA for ; Fri, 10 Mar 2017 19:24:15 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 5FNaojCSQBY7 for ; Fri, 10 Mar 2017 19:24:14 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by whitealder.osuosl.org (Postfix) with ESMTPS id B71D789C36 for ; Fri, 10 Mar 2017 19:24:14 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Mar 2017 11:24:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.36,142,1486454400"; d="scan'208"; a="1107116174" Received: from bimmy.jf.intel.com (HELO bimmy.linux1.jf.intel.com) ([10.166.35.87]) by orsmga001.jf.intel.com with ESMTP; 10 Mar 2017 11:24:12 -0800 From: Bimmy Pujari To: intel-wired-lan@lists.osuosl.org Date: Fri, 10 Mar 2017 12:22:03 -0800 Message-Id: <1489177325-13156-5-git-send-email-bimmy.pujari@intel.com> X-Mailer: git-send-email 2.4.11 In-Reply-To: <1489177325-13156-1-git-send-email-bimmy.pujari@intel.com> References: <1489177325-13156-1-git-send-email-bimmy.pujari@intel.com> Cc: Christopher Bednarz Subject: [Intel-wired-lan] [next PATCH S62 4/6] i40e: Check for new arq elements before leaving the adminq subtask loop X-BeenThere: intel-wired-lan@lists.osuosl.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-wired-lan-bounces@lists.osuosl.org Sender: "Intel-wired-lan" From: "Christopher Bednarz" Fix a case where we miss an arq element if a new one is added before we enable interrupts and exit the arq subtask loop. This occurs frequently with Rdma running on Windows VF and causes long delays that prevent SMB from establishing connections. Signed-off-by: Christopher N Bednarz Change-ID: I3e1c8b2b960c12857d9b8275bea2c1563674392e Tested-by: Andrew Bowers --- drivers/net/ethernet/intel/i40e/i40e_main.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c index 804f41a..bab9337 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_main.c +++ b/drivers/net/ethernet/intel/i40e/i40e_main.c @@ -6524,9 +6524,11 @@ static void i40e_clean_adminq_subtask(struct i40e_pf *pf) opcode); break; } - } while (pending && (i++ < pf->adminq_work_limit)); + } while (i++ < pf->adminq_work_limit); + + if (i < pf->adminq_work_limit) + clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state); - clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state); /* re-enable Admin queue interrupt cause */ val = rd32(hw, I40E_PFINT_ICR0_ENA); val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;