diff --git a/hostapd/config_file.c b/hostapd/config_file.c
old mode 100644
new mode 100755
index daaa484f2..75bd4915a
--- a/hostapd/config_file.c
+++ b/hostapd/config_file.c
@@ -1384,6 +1384,112 @@ static u8 set_he_cap(int val, u8 mask)
 {
 	return (u8) (mask & (val << ffs(mask)));
 }
+
+static int hostapd_config_he_capab(struct hostapd_config *conf,
+				    const char *capab)
+{
+	/* HE MAC Capabilities Information field */
+	if (os_strstr(capab, "[PLUS_HTC_HE_SUPPORT]"))
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP0_IDX] |=
+			HE_MAC_CAP0_HTC_HE_SUPPORT;
+	if (os_strstr(capab, "[TWT_REQUESTER_SUPPORT]"))
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP0_IDX] |=
+			HE_MAC_CAP0_TWT_REQUESTER_SUPPORT;
+	if (os_strstr(capab, "[TWT_RESPONDER_SUPPORT]"))
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP0_IDX] |=
+			HE_MAC_CAP0_TWT_RESPONDER_SUPPORT;
+	if (os_strstr(capab, "[ALL_ACK_SUPPORT]"))
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP2_IDX] |=
+			HE_MAC_CAP2_ALL_ACK_SUPPORT;
+	if (os_strstr(capab, "[BSR_SUPPORT]"))
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP2_IDX] |=
+			HE_MAC_CAP2_BSR_SUPPORT;
+	if (os_strstr(capab, "[BROADCAST_TWT_SUPPORT]"))
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP2_IDX] |=
+			HE_MAC_CAP2_BROADCAST_TWT_SUPPORT;
+	if (os_strstr(capab, "[32BIT_BA_BITMAP_SUPPORT]"))
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP2_IDX] |=
+			HE_MAC_CAP2_32BIT_BA_BITMAP_SUPPORT;
+	if (os_strstr(capab, "[MU_CASCADING_SUPPORT]"))
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP2_IDX] |=
+			HE_MAC_CAP2_MU_CASCADING_SUPPORT;
+	if (os_strstr(capab, "[ACK_ENABLED_AGGREGATION_SUPPORT]"))
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP2_IDX] |=
+			HE_MAC_CAP2_ACK_ENABLED_AGGREGATION_SUPPORT;
+	if (os_strstr(capab, "[OM_CONTROL_SUPPORT]"))
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP3_IDX] |=
+			HE_MAC_CAP3_OM_CONTROL_SUPPORT;
+	if (os_strstr(capab, "[OFDMA_RA_SUPPORT]"))
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP3_IDX] |=
+			HE_MAC_CAP3_OFDMA_RA_SUPPORT;
+	if (os_strstr(capab, "[A_MSDU_FRAGMENTATION_SUPPORT]"))
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP3_IDX] |=
+			HE_MAC_CAP3_AMSDU_FRGMENTATION_SUPPORT;
+	if (os_strstr(capab, "[FLEXIBLE_TWT_SCHEDULE_SUPPORT]"))
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP3_IDX] |=
+			HE_MAC_CAP3_FLEXIBLE_TWT_SCHEDULE_SUPPORT;
+	if (os_strstr(capab, "[RX_CONTROL_FRAME_TO_MULTIBSS]"))
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP3_IDX] |=
+			HE_MAC_CAP3_RX_CONTROL_FRAME_TO_MULTIBSS;
+	if (os_strstr(capab, "[BSRP_A_MPDU_AGGREGATION]"))
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP4_IDX] |=
+			HE_MAC_CAP4_BSRP_BQRP_AMPDU_AGGREGATION;
+	if (os_strstr(capab, "[QTP_SUPPORT]"))
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP4_IDX] |=
+			HE_MAC_CAP4_QTP_SUPPORT;
+	if (os_strstr(capab, "[BQR_SUPPORT]"))
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP4_IDX] |=
+			HE_MAC_CAP4_BQR_SUPPORT;
+	if (os_strstr(capab, "[AMSDU_IN_AMPDU SUPPORT]"))
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP4_IDX] |=
+			HE_MAC_CAP4_AMSDU_IN_AMPDU_SUPPORT;
+
+	/* HE PHY Capabilities Information field */
+	if (os_strstr(capab, "[DEVICE_CLASS]"))
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP1_IDX] |=
+			HE_PHY_CAP1_DEVICE_CLASS;
+	if (os_strstr(capab, "[LDPC_CODING_IN_PAYLOAD]"))
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP1_IDX] |=
+			HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD;
+	if (os_strstr(capab, "[NG_16_CAPABLE_SU_FEEDBACK]"))
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP5_IDX] |=
+			HE_PHY_CAP5_NG_16_FOR_SU_FB_SUPPORT;
+	if (os_strstr(capab, "[NG_16_MU_FEEDBACK]"))
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP5_IDX] |=
+			HE_PHY_CAP5_NG_16_FOR_MU_FB_SUPPORT;
+	if (os_strstr(capab, "[CODEBOOK_SIZE42_FOR_SU_SUPPORT]"))
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP6_IDX] |=
+			HE_PHY_CAP6_CODEBOOK_SIZE42_FOR_SU_SUPPORT;
+	if (os_strstr(capab, "[CODEBOOK_SIZE75_FOR_MU_SUPPORT]"))
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP6_IDX] |=
+			HE_PHY_CAP6_CODEBOOK_SIZE75_FOR_MU_SUPPORT;
+	if (os_strstr(capab, "[PPE_THRESHOLD_PRESENT]"))
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP6_IDX] |=
+			HE_PHY_CAP6_PPE_THRESHOLD_PRESENT;
+	if (os_strstr(capab, "[SRP_BASED_SR_SUPPORT]"))
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP7_IDX] |=
+			HE_PHY_CAP7_SRP_BASED_SR_SUPPORT;
+	if (os_strstr(capab, "[POWER_BOOST_FACTOR_ALPHA_SUPPORT]"))
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP7_IDX] |=
+			HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPPORT;
+	if (os_strstr(capab, "[SU_PPDU_AND_HE_MU_PPDU_WITH_4X_HE_LTF_08US_GI]"))
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP7_IDX] |=
+			HE_PHY_CAP7_SU_PPDU_AND_HE_MU_WITH_4X_HE_LTF_0_8US_GI;
+	if (os_strstr(capab, "[ER_SU_PPDU_WITH_4X_HE_LTF_08US_GI]"))
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP8_IDX] |=
+			HE_PHY_CAP8_HE_ER_SU_PPDU_4X_HE_LTF_0_8_US_GI;
+	if (os_strstr(capab, "[TRIGGERED_SU_BEAMFORMING_FEEDBACK]"))
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP6_IDX] |=
+			HE_PHY_CAP6_TRIGGERED_SU_BEAMFORMING_FEEDBACK;
+	if (os_strstr(capab, "[TRIGGERED_CQI_FEEDBACK]"))
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP6_IDX] |=
+			HE_PHY_CAP6_TRIGGERED_CQI_FEEDBACK;
+	if (os_strstr(capab, "[PARTIAL_BANDWIDTH_EXTENDED_RANGE]"))
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP6_IDX] |=
+			HE_PHY_CAP6_PARTIAL_BANDWIDTH_EXTENDED_RANGE;
+
+	return 0;
+}
 #endif /* CONFIG_IEEE80211AX */
 
 
@@ -3391,12 +3497,242 @@ static int hostapd_config_fill(struct hostapd_config *conf,
 #ifdef CONFIG_IEEE80211AX
 	} else if (os_strcmp(buf, "ieee80211ax") == 0) {
 		conf->ieee80211ax = atoi(pos);
-	} else if (os_strcmp(buf, "he_su_beamformer") == 0) {
-		conf->he_phy_capab.he_su_beamformer = atoi(pos);
-	} else if (os_strcmp(buf, "he_su_beamformee") == 0) {
-		conf->he_phy_capab.he_su_beamformee = atoi(pos);
-	} else if (os_strcmp(buf, "he_mu_beamformer") == 0) {
-		conf->he_phy_capab.he_mu_beamformer = atoi(pos);
+	} else if (os_strcmp(buf, "he_capab") == 0) {
+		if (hostapd_config_he_capab(conf, pos) < 0) {
+			wpa_printf(MSG_ERROR, "Line %d: invalid he_capab",
+				   line);
+			return 1;
+		}
+	} else if (os_strcmp(buf, "he_mac_fragmentation") == 0) {
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP0_IDX] |=
+			set_he_cap(atoi(pos), HE_MAC_CAP0_FRAGMENTATION_SUPPORT);
+	} else if (os_strcmp(buf, "he_mac_max_num_of_frag_msdus") == 0) {
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP0_IDX] |=
+			set_he_cap(atoi(pos), HE_MAC_CAP0_MAX_NUM_OF_FRAG_MSDU);
+	} else if (os_strcmp(buf, "he_mac_minimum_fragment_size") == 0) {
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP1_IDX] |=
+			set_he_cap(atoi(pos), HE_MAC_CAP1_MINIMUM_FRAGMENT_SIZE);
+	} else if (os_strcmp(buf, "he_mac_trigger_frame_mac_pad_dur") == 0) {
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP1_IDX] |=
+			set_he_cap(atoi(pos), HE_MAC_CAP1_TRIGGER_FRAME_MAC_PAD_DUR);
+	} else if (os_strcmp(buf, "he_mac_multi_tid_aggr_support") == 0) {
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP1_IDX] |=
+			set_he_cap(atoi(pos), HE_MAC_CAP1_MULTI_TID_AGGR_RX_SUPPORT);
+	} else if (os_strcmp(buf, "he_mac_he_link_adaptation") == 0) {
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP1_IDX] |=
+			set_he_cap(atoi(pos), HE_MAC_CAP1_HE_LINK_ADAPTION_SUPPORT);
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP2_IDX] |=
+			set_he_cap(atoi(pos) >> 1, HE_MAC_CAP2_HE_LINK_ADAPTION_SUPPORT);
+	} else if (os_strcmp(buf, "he_mac_max_a_mpdu_length_exp") == 0) {
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP3_IDX] |=
+			set_he_cap(atoi(pos), HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT);
+	} else if (os_strcmp(buf, "he_mac_multi_tid_aggr_tx_support") == 0) {
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP4_IDX] |=
+			set_he_cap(atoi(pos), HE_MAC_CAP4_MULTI_TID_AGGR_TX_SUPPORT);
+		conf->he_capab.he_mac_capab_info[HE_MACCAP_CAP5_IDX] |=
+			set_he_cap(atoi(pos) >> 1, HE_MAC_CAP5_MULTI_TID_AGGR_TX_SUPPORT);
+	} else if (os_strcmp(buf, "he_phy_channel_width_set") == 0) {
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP0_IDX] |=
+			set_he_cap(atoi(pos), HE_PHY_CAP0_CHANNEL_WIDTH_SET);
+	} else if (os_strcmp(buf, "he_phy_preamble_puncturing_rx") == 0) {
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP1_IDX] |=
+			set_he_cap(atoi(pos), HE_PHY_CAP1_PUN_PREAM_RX);
+	} else if (os_strcmp(buf, "he_phy_su_ppdu_1x_he_ltf_08_us_gi") == 0) {
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP1_IDX] |=
+			set_he_cap(atoi(pos), HE_PHY_CAP1_SU_PPDU_1XHE_LTF_0_8US_GI);
+	} else if (os_strcmp(buf, "he_phy_ndp_4x_he_ltf_and_32_us_gi") == 0) {
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP2_IDX] |=
+			set_he_cap(atoi(pos), HE_PHY_CAP2_NDP_4X_HE_LTF_AND_3_2MS_GI);
+	} else if (os_strcmp(buf, "he_phy_stbc_tx_less_or_equal_80mhz") == 0) {
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP2_IDX] |=
+			set_he_cap(atoi(pos), HE_PHY_CAP2_STBC_TX_LESS_OR_EQUAL_80MHz);
+	} else if (os_strcmp(buf, "he_phy_stbc_rx_less_or_equal_80mhz") == 0) {
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP2_IDX] |=
+			set_he_cap(atoi(pos), HE_PHY_CAP2_STBC_RX_LESS_OR_EQUAL_80MHz);
+	} else if (os_strcmp(buf, "he_phy_doppler_rx") == 0) {
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP2_IDX] |=
+			set_he_cap(atoi(pos), HE_PHY_CAP2_DOPPLER_RX);
+	} else if (os_strcmp(buf, "he_phy_doppler_tx") == 0) {
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP2_IDX] |=
+			set_he_cap(atoi(pos), HE_PHY_CAP2_DOPPLER_TX);
+	} else if (os_strcmp(buf, "he_phy_full_bandwidth_ul_mu_mimo") == 0) {
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP2_IDX] |=
+			set_he_cap(atoi(pos), HE_PHY_CAP2_FULL_BANDWIDTH_UL_MU_MIMO);
+	} else if (os_strcmp(buf, "he_phy_partial_bandwidth_ul_mu_mimo") == 0) {
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP2_IDX] |=
+			set_he_cap(atoi(pos), HE_PHY_CAP2_PARTIAL_BANDWIDTH_UL_MU_MIMO);
+	} else if (os_strcmp(buf, "he_phy_dcm_max_constellation_tx") == 0) {
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP3_IDX] |=
+			set_he_cap(atoi(pos), HE_PHY_CAP3_DCM_MAX_CONSTELLATION_TX);
+	} else if (os_strcmp(buf, "he_phy_dcm_max_constellation_rx") == 0) {
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP3_IDX] |=
+			set_he_cap(atoi(pos), HE_PHY_CAP3_DCM_MAX_CONSTELLATION_RX);
+	} else if (os_strcmp(buf, "he_phy_dcm_max_nss_tx") == 0) {
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP3_IDX] |=
+			set_he_cap(atoi(pos), HE_PHY_CAP3_DCM_MAX_NSS_TX);
+	} else if (os_strcmp(buf, "he_phy_dcm_max_nss_rx") == 0) {
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP3_IDX] |=
+			set_he_cap(atoi(pos), HE_PHY_CAP3_DCM_MAX_NSS_RX);
+	} else if (os_strcmp(buf, "he_phy_su_beamformer") == 0) {
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP3_IDX] |=
+			set_he_cap(atoi(pos), HE_PHY_CAP3_SU_BEAMFORMER);
+	} else if (os_strcmp(buf, "he_phy_su_beamformee") == 0) {
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP4_IDX] |=
+			set_he_cap(atoi(pos), HE_PHY_CAP4_SU_BEAMFORMEE);
+	} else if (os_strcmp(buf, "he_phy_mu_beamformer") == 0) {
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP4_IDX] |=
+			set_he_cap(atoi(pos), HE_PHY_CAP4_MU_BEAMFORMER);
+	} else if (os_strcmp(buf, "he_phy_bmformee_sts_less_or_eq_80mhz") == 0) {
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP4_IDX] |=
+			set_he_cap(atoi(pos), HE_PHY_CAP4_BF_STS_LESS_OR_EQ_80MHz);
+	} else if (os_strcmp(buf, "he_phy_bmformee_sts_greater_than_80mhz") == 0) {
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP4_IDX] |=
+			set_he_cap(atoi(pos), HE_PHY_CAP4_BF_STS_GREATER_THAN_80MHz);
+	} else if (os_strcmp(buf, "he_phy_num_sound_dim_less_or_eq_80mhz") == 0) {
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP5_IDX] |=
+			set_he_cap(atoi(pos), HE_PHY_CAP5_NUM_SOUND_DIM_LESS_80MHz);
+	} else if (os_strcmp(buf, "he_phy_num_sound_dim_greater_80mhz") == 0) {
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP5_IDX] |=
+			set_he_cap(atoi(pos), HE_PHY_CAP5_NUM_SOUND_DIM_GREAT_80MHz);
+	} else if (os_strcmp(buf, "he_phy_max_nc") == 0) {
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP7_IDX] |=
+			set_he_cap(atoi(pos), HE_PHY_CAP7_MAX_NC);
+	} else if (os_strcmp(buf, "he_phy_ng_16_capable_su_feedback") == 0) {
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP5_IDX] |=
+			set_he_cap(atoi(pos), HE_PHY_CAP5_NG_16_FOR_SU_FB_SUPPORT);
+	} else if (os_strcmp(buf, "he_phy_ng_16_mu_feedback") == 0) {
+		conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP5_IDX] |=
+			set_he_cap(atoi(pos), HE_PHY_CAP5_NG_16_FOR_MU_FB_SUPPORT);
+	} else if (os_strcmp(buf, "he_mcs_nss_rx_less_or_eq_80mhz") == 0) {
+		conf->he_capab.he_txrx_mcs_support[0] = atoi(pos) & 0xff;
+		conf->he_capab.he_txrx_mcs_support[1] = (atoi(pos) >> 8) & 0xff;
+	} else if (os_strcmp(buf, "he_mcs_nss_tx_less_or_eq_80mhz") == 0) {
+		conf->he_capab.he_txrx_mcs_support[2] = atoi(pos) & 0xff;
+		conf->he_capab.he_txrx_mcs_support[3] = (atoi(pos) >> 8) & 0xff;
+	} else if (os_strcmp(buf, "he_mcs_nss_rx_he_mcs_map_160_mhz") == 0) {
+		conf->he_capab.he_txrx_mcs_support[4] = atoi(pos) & 0xff;
+		conf->he_capab.he_txrx_mcs_support[5] = (atoi(pos) >> 8) & 0xff;
+	} else if (os_strcmp(buf, "he_mcs_nss_tx_he_mcs_map_160_mhz") == 0) {
+			conf->he_capab.he_txrx_mcs_support[6] = atoi(pos) & 0xff;
+			conf->he_capab.he_txrx_mcs_support[7] = (atoi(pos) >> 8) & 0xff;
+	} else if (os_strcmp(buf, "he_ppe_th_nss") == 0) {
+			conf->he_capab.he_ppe_thresholds[HE_PPE_CAP0_IDX] |=
+				set_he_cap(atoi(pos), HE_PPE_CAP0_NSS_M1);
+	} else if (os_strcmp(buf, "he_ppe_th_ru_index_bitmask") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP0_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP0_RU_INDEX_BITMASK);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet16_for_nss1_for_ru0") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP0_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP0_PPET16_FOR_NSS1_FOR_RU0);
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP1_IDX] |=
+			set_he_cap(atoi(pos) >> 1, HE_PPE_CAP1_PPET16_FOR_NSS1_FOR_RU0);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet16_for_nss1_for_ru1") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP1_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP1_PPET16_FOR_NSS1_FOR_RU1);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet16_for_nss1_for_ru2") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP2_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP2_PPET16_FOR_NSS1_FOR_RU2);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet16_for_nss1_for_ru3") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP3_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP3_PPET16_FOR_NSS1_FOR_RU3);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet16_for_nss2_for_ru0") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP3_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP3_PPET16_FOR_NSS2_FOR_RU0);
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP4_IDX] |=
+			set_he_cap(atoi(pos) >> 1, HE_PPE_CAP4_PPET16_FOR_NSS2_FOR_RU0);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet16_for_nss2_for_ru1") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP4_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP4_PPET16_FOR_NSS2_FOR_RU1);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet16_for_nss2_for_ru2") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP5_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP5_PPET16_FOR_NSS2_FOR_RU2);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet16_for_nss2_for_ru3") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP6_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP6_PPET16_FOR_NSS2_FOR_RU3);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet16_for_nss3_for_ru0") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP6_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP6_PPET16_FOR_NSS3_FOR_RU0);
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP7_IDX] |=
+			set_he_cap(atoi(pos) >> 1, HE_PPE_CAP7_PPET16_FOR_NSS3_FOR_RU0);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet16_for_nss3_for_ru1") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP7_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP7_PPET16_FOR_NSS3_FOR_RU1);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet16_for_nss3_for_ru2") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP8_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP8_PPET16_FOR_NSS3_FOR_RU2);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet16_for_nss3_for_ru3") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP9_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP9_PPET16_FOR_NSS3_FOR_RU3);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet16_for_nss4_for_ru0") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP9_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP9_PPET16_FOR_NSS4_FOR_RU0);
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP10_IDX] |=
+			set_he_cap(atoi(pos) >> 1, HE_PPE_CAP10_PPET16_FOR_NSS4_FOR_RU0);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet16_for_nss4_for_ru1") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP10_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP10_PPET16_FOR_NSS4_FOR_RU1);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet16_for_nss4_for_ru2") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP11_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP11_PPET16_FOR_NSS4_FOR_RU2);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet16_for_nss4_for_ru3") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP12_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP12_PPET16_FOR_NSS4_FOR_RU3);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet8_for_nss1_for_ru0") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP1_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP1_PPET8_FOR_NSS1_FOR_RU0);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet8_for_nss1_for_ru1") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP2_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP2_PPET8_FOR_NSS1_FOR_RU1);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet8_for_nss1_for_ru2") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP2_IDX] |=
+			set_he_cap(atoi(pos),HE_PPE_CAP2_PPET8_FOR_NSS1_FOR_RU2 );
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP3_IDX] |=
+			set_he_cap(atoi(pos) >> 2, HE_PPE_CAP3_PPET8_FOR_NSS1_FOR_RU2);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet8_for_nss1_for_ru3") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP3_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP3_PPET8_FOR_NSS1_FOR_RU3);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet8_for_nss2_for_ru0") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP4_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP4_PPET8_FOR_NSS2_FOR_RU0);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet8_for_nss2_for_ru1") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP5_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP5_PPET8_FOR_NSS2_FOR_RU1);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet8_for_nss2_for_ru2") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP5_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP5_PPET8_FOR_NSS2_FOR_RU2);
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP6_IDX] |=
+			set_he_cap(atoi(pos) >> 2, HE_PPE_CAP6_PPET8_FOR_NSS2_FOR_RU2);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet8_for_nss2_for_ru3") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP6_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP6_PPET8_FOR_NSS2_FOR_RU3);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet8_for_nss3_for_ru0") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP7_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP7_PPET8_FOR_NSS3_FOR_RU0);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet8_for_nss3_for_ru1") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP8_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP8_PPET8_FOR_NSS3_FOR_RU1);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet8_for_nss3_for_ru2") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP8_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP8_PPET8_FOR_NSS3_FOR_RU2);
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP9_IDX] |=
+			set_he_cap(atoi(pos) >> 2, HE_PPE_CAP9_PPET8_FOR_NSS3_FOR_RU2);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet8_for_nss3_for_ru3") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP9_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP9_PPET8_FOR_NSS3_FOR_RU3);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet8_for_nss4_for_ru0") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP10_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP10_PPET8_FOR_NSS4_FOR_RU0);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet8_for_nss4_for_ru1") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP11_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP11_PPET8_FOR_NSS4_FOR_RU1);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet8_for_nss4_for_ru2") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP11_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP11_PPET8_FOR_NSS4_FOR_RU2);
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP12_IDX] |=
+			set_he_cap(atoi(pos) >> 2, HE_PPE_CAP12_PPET8_FOR_NSS4_FOR_RU2);
+	} else if (os_strcmp(buf, "he_ppe_th_ppet8_for_nss4_for_ru3") == 0) {
+		conf->he_capab.he_ppe_thresholds[HE_PPE_CAP12_IDX] |=
+			set_he_cap(atoi(pos), HE_PPE_CAP12_PPET8_FOR_NSS4_FOR_RU3);
 	} else if (os_strcmp(buf, "he_bss_color") == 0) {
 		conf->he_op.he_bss_color = atoi(pos);
 	} else if (os_strcmp(buf, "he_default_pe_duration") == 0) {
diff --git a/hostapd/hostapd.conf b/hostapd/hostapd.conf
old mode 100644
new mode 100755
index 739d36772..f94671ca9
--- a/hostapd/hostapd.conf
+++ b/hostapd/hostapd.conf
@@ -767,20 +767,122 @@ wmm_ac_vo_acm=0
 # 1 = enabled
 #ieee80211ax=1
 
-#he_su_beamformer: HE single user beamformer support
+# he_capab: HE capabilities (list of flags)
+#
+# +HTC-HE Support: [PLUS_HTC_HE_SUPPORT]
+# Indicates support for the reception of a frame that carries an HE variant
+# HT Control field.
+# An AP sets the +HTC-HE Support subfield to 1
+#
+# Ack-Enabled Aggregation Support: [ACK_ENABLED_AGGREGATION_SUPPORT]
+# Indicates support by a STA to receive an A-MPDU that contains two or more
+# frames at least one of which solicits an Ack frame or acknowledgment context
+# in a Multi-STA BlockAck frame as (Multi-TID A-MPDU and ack-enabled AMPDU).
+# 0 = STA supports reception of this A-MPDU format
+# 1 = not supported
+#
+# OM Control Support: [OM_CONTROL_SUPPORT]
+# Indicates support for receiving an MPDU that contains an OM Control subfield
+# An AP sets the OM Control Support subfield to 1
+#
+# A-MSDU In A-MPDU Support: [AMSDU_IN_AMPDU SUPPORT]
+# Indicates support by a STA to receive an ack-enabled A-MPDU in which an
+# A-MSDU is carried in a QoS Data frame for which no block ack agreement exists
+# 0 = not supported
+# 1 = supported
+#
+# Device Class: [DEVICE_CLASS]
+# For a non-AP STA, indicates whether the STA is a Class A or a Class B device
+# Reserved for an AP.
+# 0 = Class A device
+# 1 = Class B device
+#
+# LDPC Coding In Payload: [LDPC_CODING_IN_PAYLOAD]
+# Indicates support for the transmission and reception of LDPC encoded packets
+# 0 = not supported
+# 1 = supported
+#
+# Triggered SU Beamforming Feedback: [TRIGGERED_SU_BEAMFORMING_FEEDBACK]
+# For an AP, indicates support for the reception of partial and full bandwidth
+# SU-type feedback in an HE TB sounding sequence.
+# For a non-AP STA, indicates support for the transmission of partial and full
+# bandwidth SU-type feedback in an HE TB sounding sequence.
+# 0 = not supported
+# 1 = supported
+#
+# Triggered CQI Feedback: [TRIGGERED_CQI_FEEDBACK]
+# For an AP, indicates support for the reception of partial and full bandwidth
+# CQI-only feedback in an HE TB sounding sequence.
+# For a non-AP STA, indicates support for the transmission of partial and full
+# bandwidth CQI-only feedback in an HE TB sounding sequence.
+# 0 = not supported
+# 1 = supported
+#
+# PPE Threshold Present: [PPE_THRESHOLD_PRESENT]
+# Indicates whether or not the PPE Threshold field is present.
+# 0 = PPE Threshold field is not present
+# 1 = PPE Threshold field is present
+#
+# HE ER SU PPDU With 4x HE-LTF And 0.8 us GI:
+# [ER_SU_PPDU_WITH_4X_HE_LTF_08US_GI]
+# Indicates support for the reception of an HE ER SU PPDU with 4x LTF and
+# 0.8 us guard interval duration.
+# 0 = not supported
+# 1 = supported
+#
+# HE SU PPDU And HE MU PPDU With 4x HE-LTF And 0.8 µs GI:
+# [SU_PPDU_AND_HE_MU_PPDU_WITH_4X_HE_LTF_08US_GI]
+# Indicates support for the reception of an HE SU PPDU and HE MU PPDU with 4x
+# LTF and 0.8 us guard interval duration.
+# This subfield is set to 1 if the HE ER SU PPDU With 4x HE-LTF And 0.8 µs GI subfield is 1
+# 0 = not supported
+# 1 = supported
+
+#he_mac_fragmentation = 0
+#he_mac_max_num_of_frag_msdus=7
+#he_mac_multi_tid_aggr_support=7
+#he_mac_max_a_mpdu_length_exp=2
+#he_mac_multi_tid_aggr_tx_support=2
+#he_phy_channel_width_set=7
+#he_phy_stbc_tx_less_or_equal_80mhz=1
+#he_phy_dcm_max_constellation_tx=2
+#he_phy_dcm_max_constellation_rx=2
+#he_phy_dcm_max_nss_tx=1
+#he_phy_dcm_max_nss_rx=1
+
+#he_phy_su_beamformer: HE single user beamformer support
 # 0 = not supported (default)
 # 1 = supported
-#he_su_beamformer=1
+#he_phy_su_beamformer=1
 
-#he_su_beamformee: HE single user beamformee support
+#he_phy_su_beamformee: HE single user beamformee support
 # 0 = not supported (default)
 # 1 = supported
-#he_su_beamformee=1
+#he_phy_su_beamformee=1
 
-#he_mu_beamformer: HE multiple user beamformer support
+#he_phy_mu_beamformer: HE multiple user beamformer support
 # 0 = not supported (default)
 # 1 = supported
-#he_mu_beamformer=1
+#he_phy_mu_beamformer=1
+
+#he_ppe_th_nss=3
+#he_ppe_th_ru_index_bitmask=15
+#he_ppe_th_ppet8_for_nss1_for_ru0=7
+#he_ppe_th_ppet8_for_nss1_for_ru1=7
+#he_ppe_th_ppet8_for_nss1_for_ru2=7
+#he_ppe_th_ppet8_for_nss1_for_ru3=7
+#he_ppe_th_ppet8_for_nss2_for_ru0=7
+#he_ppe_th_ppet8_for_nss2_for_ru1=7
+#he_ppe_th_ppet8_for_nss2_for_ru2=7
+#he_ppe_th_ppet8_for_nss2_for_ru3=7
+#he_ppe_th_ppet8_for_nss3_for_ru0=7
+#he_ppe_th_ppet8_for_nss3_for_ru1=7
+#he_ppe_th_ppet8_for_nss3_for_ru2=7
+#he_ppe_th_ppet8_for_nss3_for_ru3=7
+#he_ppe_th_ppet8_for_nss4_for_ru0=7
+#he_ppe_th_ppet8_for_nss4_for_ru1=7
+#he_ppe_th_ppet8_for_nss4_for_ru2=7
+#he_ppe_th_ppet8_for_nss4_for_ru3=7
 
 # he_bss_color: BSS color
 # 0 = no BSS color (default)
diff --git a/src/ap/ap_config.h b/src/ap/ap_config.h
old mode 100644
new mode 100755
index 990d0d1b5..84082e37e
--- a/src/ap/ap_config.h
+++ b/src/ap/ap_config.h
@@ -704,15 +704,6 @@ struct hostapd_bss_config {
 };
 
 /**
- * struct he_phy_capabilities_info - HE PHY capabilities
- */
-struct he_phy_capabilities_info {
-	Boolean he_su_beamformer;
-	Boolean he_su_beamformee;
-	Boolean he_mu_beamformer;
-};
-
-/**
  * struct he_operation - HE operation
  */
 struct he_operation {
@@ -841,7 +832,7 @@ struct hostapd_config {
 
 	int ieee80211ax;
 #ifdef CONFIG_IEEE80211AX
-	struct he_phy_capabilities_info he_phy_capab;
+	struct ieee80211_he_capabilities he_capab;
 	struct he_operation he_op;
 	struct ieee80211_he_mu_edca_parameter_set he_mu_edca;
 #endif /* CONFIG_IEEE80211AX */
diff --git a/src/ap/ieee802_11_he.c b/src/ap/ieee802_11_he.c
old mode 100644
new mode 100755
index 072135863..68ce77e03
--- a/src/ap/ieee802_11_he.c
+++ b/src/ap/ieee802_11_he.c
@@ -20,30 +20,59 @@ u8 * hostapd_eid_he_capab(struct hostapd_data *hapd, u8 *eid)
 {
 	struct ieee80211_he_capabilities *cap;
 	u8 *pos = eid;
+	u8 *he_cap;
+	u8 he_txrx_mcs_size;
+	u8 size;
 
 	if (!hapd->iface->current_mode)
 		return eid;
 
-	*pos++ = WLAN_EID_EXTENSION;
-	*pos++ = 1 + sizeof(struct ieee80211_he_capabilities);
-	*pos++ = WLAN_EID_EXT_HE_CAPABILITIES;
-
-	cap = (struct ieee80211_he_capabilities *) pos;
-	os_memset(cap, 0, sizeof(*cap));
+	if(hapd->iface->conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP0_IDX] &
+			HE_PHY_CAP0_CHANNEL_WIDTH_SET_B3)
+		he_txrx_mcs_size = sizeof(cap->he_txrx_mcs_support);
+	else if(hapd->iface->conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP0_IDX] &
+			HE_PHY_CAP0_CHANNEL_WIDTH_SET_B2)
+		he_txrx_mcs_size = 2*(sizeof(cap->he_txrx_mcs_support)/3);
+	else
+		he_txrx_mcs_size = sizeof(cap->he_txrx_mcs_support)/3;
 
-	if (hapd->iface->conf->he_phy_capab.he_su_beamformer)
-		cap->he_phy_capab_info[HE_PHYCAP_SU_BEAMFORMER_CAPAB_IDX] |=
-			HE_PHYCAP_SU_BEAMFORMER_CAPAB;
+	size = sizeof(cap->he_mac_capab_info) +
+			sizeof(cap->he_phy_capab_info) +
+			he_txrx_mcs_size;
 
-	if (hapd->iface->conf->he_phy_capab.he_su_beamformee)
-		cap->he_phy_capab_info[HE_PHYCAP_SU_BEAMFORMEE_CAPAB_IDX] |=
-			HE_PHYCAP_SU_BEAMFORMEE_CAPAB;
+	if(hapd->iface->conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP6_IDX] &
+		HE_PHY_CAP6_PPE_THRESHOLD_PRESENT)
+		size += sizeof(cap->he_ppe_thresholds) ;
 
-	if (hapd->iface->conf->he_phy_capab.he_mu_beamformer)
-		cap->he_phy_capab_info[HE_PHYCAP_MU_BEAMFORMER_CAPAB_IDX] |=
-			HE_PHYCAP_MU_BEAMFORMER_CAPAB;
+	*pos++ = WLAN_EID_EXTENSION;
+	*pos++ = 1 + size;
+	*pos++ = WLAN_EID_EXT_HE_CAPABILITIES;
 
-	pos += sizeof(*cap);
+	he_cap = pos;
+	os_memset(he_cap, 0, size);
+	os_memcpy(he_cap,
+		&hapd->iface->conf->he_capab.he_mac_capab_info,
+		sizeof(cap->he_mac_capab_info));
+
+	he_cap = (u8 *) (he_cap + sizeof(cap->he_mac_capab_info));
+	os_memcpy(he_cap,
+		&hapd->iface->conf->he_capab.he_phy_capab_info,
+		sizeof(cap->he_phy_capab_info));
+
+	he_cap = (u8 *) (he_cap + sizeof(cap->he_phy_capab_info));
+	os_memcpy(he_cap,
+		&hapd->iface->conf->he_capab.he_txrx_mcs_support,
+		he_txrx_mcs_size);
+
+	if(hapd->iface->conf->he_capab.he_phy_capab_info[HE_PHYCAP_CAP6_IDX] &
+			HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) {
+		he_cap = (u8 *) (he_cap + he_txrx_mcs_size);
+		os_memcpy(he_cap,
+			&hapd->iface->conf->he_capab.he_ppe_thresholds,
+			sizeof(cap->he_ppe_thresholds));
+	}
+	wpa_hexdump(MSG_DEBUG, "hostapd_eid_he_capab:", pos, size);
+	pos += size;
 
 	return pos;
 }
diff --git a/src/common/ieee802_11_defs.h b/src/common/ieee802_11_defs.h
old mode 100644
new mode 100755
index cc512c6c9..809564dad
--- a/src/common/ieee802_11_defs.h
+++ b/src/common/ieee802_11_defs.h
@@ -2108,8 +2108,9 @@ enum nr_chan_width {
 struct ieee80211_he_capabilities {
 	u8 he_mac_capab_info[6];
 	u8 he_phy_capab_info[11];
-	u8 he_txrx_mcs_support[12]; /* TODO: 4, 8, or 12 octets */
+	u8 he_txrx_mcs_support[12];
 	/* PPE Thresholds (optional) */
+	u8 he_ppe_thresholds[13]; /* TODO: Considering only 4 NSTS */
 } STRUCT_PACKED;
 
 struct ieee80211_he_operation {
@@ -2122,13 +2123,215 @@ struct ieee80211_he_operation {
 	/* Followed by conditional MaxBSSID Indicator subfield (u8) */
 } STRUCT_PACKED;
 
-/* HE Capabilities Information defines */
-#define HE_PHYCAP_SU_BEAMFORMER_CAPAB_IDX	3
-#define HE_PHYCAP_SU_BEAMFORMER_CAPAB		((u8) BIT(7))
-#define HE_PHYCAP_SU_BEAMFORMEE_CAPAB_IDX	4
-#define HE_PHYCAP_SU_BEAMFORMEE_CAPAB		((u8) BIT(0))
-#define HE_PHYCAP_MU_BEAMFORMER_CAPAB_IDX	4
-#define HE_PHYCAP_MU_BEAMFORMER_CAPAB		((u8) BIT(1))
+/* IEEE 802.11AX DRAFT VER 3.0 */
+/* HE MAC Capabilities Information field defines */
+#define HE_MACCAP_CAP0_IDX 0
+#define HE_MAC_CAP0_HTC_HE_SUPPORT ((u8) BIT(0))
+#define HE_MAC_CAP0_TWT_REQUESTER_SUPPORT ((u8) BIT(1))
+#define HE_MAC_CAP0_TWT_RESPONDER_SUPPORT ((u8) BIT(2))
+#define HE_MAC_CAP0_FRAGMENTATION_SUPPORT ((u8) (BIT(3) | BIT(4)))
+#define HE_MAC_CAP0_MAX_NUM_OF_FRAG_MSDU ((u8) (BIT(5) | BIT(6) | BIT(7)))
+
+#define HE_MACCAP_CAP1_IDX 1
+#define HE_MAC_CAP1_MINIMUM_FRAGMENT_SIZE ((u8) (BIT(0) | BIT(1)))
+#define HE_MAC_CAP1_TRIGGER_FRAME_MAC_PAD_DUR ((u8) (BIT(2) | BIT(3)))
+#define HE_MAC_CAP1_MULTI_TID_AGGR_RX_SUPPORT ((u8) (BIT(4) | BIT(5) | BIT(6)))
+/* HE_MACCAP_HE_LINK_ADAPTION_SUPPORT  B15, B16 */
+#define HE_MAC_CAP1_HE_LINK_ADAPTION_SUPPORT ((u8) BIT(7))
+
+#define HE_MACCAP_CAP2_IDX 2
+#define HE_MAC_CAP2_HE_LINK_ADAPTION_SUPPORT ((u8) BIT(0))
+#define HE_MAC_CAP2_ALL_ACK_SUPPORT ((u8) BIT(1))
+#define HE_MAC_CAP2_TRS_SUPPORT ((u8) BIT(2))
+#define HE_MAC_CAP2_BSR_SUPPORT ((u8) BIT(3))
+#define HE_MAC_CAP2_BROADCAST_TWT_SUPPORT ((u8) BIT(4))
+#define HE_MAC_CAP2_32BIT_BA_BITMAP_SUPPORT ((u8) BIT(5))
+#define HE_MAC_CAP2_MU_CASCADING_SUPPORT ((u8) BIT(6))
+#define HE_MAC_CAP2_ACK_ENABLED_AGGREGATION_SUPPORT ((u8) BIT(7))
+
+#define HE_MACCAP_CAP3_IDX 3
+/* B24 - Reserved */
+#define HE_MAC_CAP3_OM_CONTROL_SUPPORT ((u8) BIT(1))
+#define HE_MAC_CAP3_OFDMA_RA_SUPPORT ((u8) BIT(2))
+#define HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT ((u8) (BIT(3) | BIT(4)))
+#define HE_MAC_CAP3_AMSDU_FRGMENTATION_SUPPORT ((u8) BIT(5))
+#define HE_MAC_CAP3_FLEXIBLE_TWT_SCHEDULE_SUPPORT ((u8) BIT(6))
+#define HE_MAC_CAP3_RX_CONTROL_FRAME_TO_MULTIBSS ((u8) BIT(7))
+
+#define HE_MACCAP_CAP4_IDX 4
+#define HE_MAC_CAP4_BSRP_BQRP_AMPDU_AGGREGATION ((u8) BIT(0))
+#define HE_MAC_CAP4_QTP_SUPPORT ((u8) BIT(1))
+#define HE_MAC_CAP4_BQR_SUPPORT ((u8) BIT(2))
+#define HE_MAC_CAP4_SRP_RESPONDER ((u8) BIT(3))
+#define HE_MAC_CAP4_NDP_FEEDBACK_REPORT_SUPPORT ((u8) BIT(4))
+#define HE_MAC_CAP4_OPS_SUPPORT ((u8) BIT(5))
+#define HE_MAC_CAP4_AMSDU_IN_AMPDU_SUPPORT ((u8) BIT(6))
+/* HE_MACCAP_MULTI_TID_AGGREGATION_TX_SUPPORT B39, B40, B41 */
+#define HE_MAC_CAP4_MULTI_TID_AGGR_TX_SUPPORT ((u8) (BIT(7)))
+
+#define HE_MACCAP_CAP5_IDX 5
+#define HE_MAC_CAP5_MULTI_TID_AGGR_TX_SUPPORT ((u8) (BIT(0) | BIT(1)))
+#define HE_MAC_CAP5_HE_SUBCHANNEL_SELE_TRANS_SUP ((u8) BIT(2))
+#define HE_MAC_CAP5_UL_2X996TONE_RU_SUPPORT ((u8) BIT(3))
+#define HE_MAC_CAP5_OM_CONTROL_UL_MU_DATA_DIS_RX_SUP ((u8) BIT(4))
+/* B45..B47 - Reserved */
+
+/* HE PHY Capabilities Information field defines */
+/* B0 - Reserved */
+#define HE_PHYCAP_CAP0_IDX 0
+#define HE_PHY_CAP0_CHANNEL_WIDTH_SET ((u8) (BIT(1) | BIT(2) | BIT(3) | \
+		BIT(4) | BIT(5) | BIT(6) | BIT(7)))
+#define HE_PHY_CAP0_CHANNEL_WIDTH_SET_B0 (u8) BIT(1)
+#define HE_PHY_CAP0_CHANNEL_WIDTH_SET_B1 (u8) BIT(2)
+#define HE_PHY_CAP0_CHANNEL_WIDTH_SET_B2 (u8) BIT(3)
+#define HE_PHY_CAP0_CHANNEL_WIDTH_SET_B3 (u8) BIT(4)
+#define HE_PHY_CAP0_CHANNEL_WIDTH_SET_B4 (u8) BIT(5)
+#define HE_PHY_CAP0_CHANNEL_WIDTH_SET_B5 (u8) BIT(6)
+#define HE_PHY_CAP0_CHANNEL_WIDTH_SET_B6 (u8) BIT(7)
+
+#define HE_PHYCAP_CAP1_IDX 1
+#define HE_PHY_CAP1_PUN_PREAM_RX ((u8) (BIT(0) | BIT(1) | BIT(2) | BIT(3)))
+#define HE_PHY_CAP1_DEVICE_CLASS ((u8) BIT(4))
+#define HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD ((u8) BIT(5))
+#define HE_PHY_CAP1_SU_PPDU_1XHE_LTF_0_8US_GI ((u8) BIT(6))
+/* HE_PHYCAP_MIDAMBLE_TXRX_MAX__NSTS B15 B16 */
+#define HE_PHY_CAP1_MIDAMBLE_TXRX_MAX__NSTS_PART1 ((u8) BIT(7))
+
+#define HE_PHYCAP_CAP2_IDX 2
+#define HE_PHY_CAP2_MIDAMBLE_TXRX_MAX__NSTS_PART2 ((u8) BIT(0))
+#define HE_PHY_CAP2_NDP_4X_HE_LTF_AND_3_2MS_GI ((u8) BIT(1))
+#define HE_PHY_CAP2_STBC_TX_LESS_OR_EQUAL_80MHz ((u8) BIT(2))
+#define HE_PHY_CAP2_STBC_RX_LESS_OR_EQUAL_80MHz ((u8) BIT(3))
+#define HE_PHY_CAP2_DOPPLER_TX ((u8) BIT(4))
+#define HE_PHY_CAP2_DOPPLER_RX ((u8) BIT(5))
+#define HE_PHY_CAP2_FULL_BANDWIDTH_UL_MU_MIMO ((u8) BIT(6))
+#define HE_PHY_CAP2_PARTIAL_BANDWIDTH_UL_MU_MIMO ((u8) BIT(7))
+
+#define HE_PHYCAP_CAP3_IDX 3
+#define HE_PHY_CAP3_DCM_MAX_CONSTELLATION_TX ((u8) (BIT(0) | BIT(1)))
+#define HE_PHY_CAP3_DCM_MAX_NSS_TX ((u8) BIT(2))
+#define HE_PHY_CAP3_DCM_MAX_CONSTELLATION_RX ((u8) (BIT(3) | BIT(4)))
+#define HE_PHY_CAP3_DCM_MAX_NSS_RX ((u8) BIT(5))
+#define HE_PHY_CAP3_RX_HE_MUPPDU_FROM_NON_AP_STA ((u8) BIT(6))
+#define HE_PHY_CAP3_SU_BEAMFORMER ((u8) BIT(7))
+
+#define HE_PHYCAP_CAP4_IDX 4
+#define HE_PHY_CAP4_SU_BEAMFORMEE ((u8) BIT(0))
+#define HE_PHY_CAP4_MU_BEAMFORMER ((u8) BIT(1))
+#define HE_PHY_CAP4_BF_STS_LESS_OR_EQ_80MHz ((u8) (BIT(2) | BIT(3) | BIT(4)))
+#define HE_PHY_CAP4_BF_STS_GREATER_THAN_80MHz ((u8) (BIT(5) | BIT(6) | BIT(7)))
+
+#define HE_PHYCAP_CAP5_IDX 5
+#define HE_PHY_CAP5_NUM_SOUND_DIM_LESS_80MHz ((u8) (BIT(0) | BIT(1) | BIT(2)))
+#define HE_PHY_CAP5_NUM_SOUND_DIM_GREAT_80MHz ((u8) (BIT(3) | BIT(4) | BIT(5)))
+#define HE_PHY_CAP5_NG_16_FOR_SU_FB_SUPPORT ((u8) BIT(6))
+#define HE_PHY_CAP5_NG_16_FOR_MU_FB_SUPPORT ((u8) BIT(7))
+
+#define HE_PHYCAP_CAP6_IDX 6
+#define HE_PHY_CAP6_CODEBOOK_SIZE42_FOR_SU_SUPPORT ((u8) BIT(0))
+#define HE_PHY_CAP6_CODEBOOK_SIZE75_FOR_MU_SUPPORT ((u8) BIT(1))
+#define HE_PHY_CAP6_TRIGGERED_SU_BEAMFORMING_FEEDBACK ((u8) BIT(2))
+#define HE_PHY_CAP6_TRIGGERED_MU_BEAMFORMING_PARTIAL_BW_FEEDBACK ((u8) BIT(3))
+#define HE_PHY_CAP6_TRIGGERED_CQI_FEEDBACK ((u8) BIT(4))
+#define HE_PHY_CAP6_PARTIAL_BANDWIDTH_EXTENDED_RANGE ((u8) BIT(5))
+#define HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MU_MIMO ((u8) BIT(6))
+#define HE_PHY_CAP6_PPE_THRESHOLD_PRESENT ((u8) BIT(7))
+
+#define HE_PHYCAP_CAP7_IDX 7
+#define HE_PHY_CAP7_SRP_BASED_SR_SUPPORT ((u8) BIT(0))
+#define HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPPORT ((u8) BIT(1))
+#define HE_PHY_CAP7_SU_PPDU_AND_HE_MU_WITH_4X_HE_LTF_0_8US_GI ((u8) BIT(2))
+#define HE_PHY_CAP7_MAX_NC ((u8) (BIT(3) | BIT(4) | BIT(5)))
+#define HE_PHY_CAP7_STBC_TX_GREATER_THAN_80MHz ((u8) BIT(6))
+#define HE_PHY_CAP7_STBC_RX_GREATER_THAN_80MHz ((u8) BIT(7))
+
+#define HE_PHYCAP_CAP8_IDX 8
+#define HE_PHY_CAP8_HE_ER_SU_PPDU_4X_HE_LTF_0_8_US_GI ((u8) BIT(0))
+#define HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_2_4_GHZ_BAND ((u8) BIT(1))
+#define HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU ((u8) BIT(2))
+#define HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU ((u8) BIT(3))
+#define HE_PHY_CAP8_HE_ER_SU_PPDU_1X_HE_LTF_0_8_US_GI ((u8) BIT(4))
+#define HE_PHY_CAP8_MIDAMBLE_TX_RX_2X_AND_1X_HE_LTF ((u8) BIT(5))
+#define HE_PHY_CAP8_DCM_MAX_BW ((u8) (BIT(6) | BIT(7)))
+
+#define HE_PHYCAP_CAP9_IDX 9
+#define HE_PHY_CAP9_LONGER_THAN_16_HE_SIGB_OFDM_SYMBOLS_SUPPORT ((u8) BIT(0))
+#define HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK ((u8) BIT(1))
+#define HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU_SUPPORT ((u8) BIT(2))
+#define HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU_SUPPORT ((u8) BIT(3))
+#define HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_PPDU_NON_COMP_SIGB ((u8) BIT(4))
+#define HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_PPDU_COMP_SIGB ((u8) BIT(5))
+/* B78..B87 - Reserved */
+
+/* HE PPE Thresholds field */
+#define HE_PPE_CAP0_IDX 0
+#define HE_PPE_CAP0_NSS_M1 ((u8) (BIT(0) | BIT(1) | BIT(2)))
+#define HE_PPE_CAP0_RU_INDEX_BITMASK ((u8) (BIT(3) | BIT(4) | BIT(5) | BIT(6)))
+#define HE_PPE_CAP0_PPET16_FOR_NSS1_FOR_RU0 ((u8) BIT(7))
+
+#define HE_PPE_CAP1_IDX 1
+#define HE_PPE_CAP1_PPET16_FOR_NSS1_FOR_RU0 ((u8) (BIT(0) | BIT(1)))
+#define HE_PPE_CAP1_PPET8_FOR_NSS1_FOR_RU0 ((u8) (BIT(2) | BIT(3) | BIT(4)))
+#define HE_PPE_CAP1_PPET16_FOR_NSS1_FOR_RU1 ((u8) (BIT(5) | BIT(6) | BIT(7)))
+
+#define HE_PPE_CAP2_IDX 2
+#define HE_PPE_CAP2_PPET8_FOR_NSS1_FOR_RU1 ((u8) (BIT(0) | BIT(1) | BIT(2)))
+#define HE_PPE_CAP2_PPET16_FOR_NSS1_FOR_RU2 ((u8) (BIT(3) | BIT(4) | BIT(5)))
+#define HE_PPE_CAP2_PPET8_FOR_NSS1_FOR_RU2 ((u8) (BIT(6) | BIT(7)))
+
+#define HE_PPE_CAP3_IDX 3
+#define HE_PPE_CAP3_PPET8_FOR_NSS1_FOR_RU2 (u8) BIT(0)
+#define HE_PPE_CAP3_PPET16_FOR_NSS1_FOR_RU3 ((u8) (BIT(1) | BIT(2) | BIT(3)))
+#define HE_PPE_CAP3_PPET8_FOR_NSS1_FOR_RU3 ((u8) (BIT(4) | BIT(5) | BIT(6)))
+#define HE_PPE_CAP3_PPET16_FOR_NSS2_FOR_RU0 ((u8) BIT(7))
+
+#define HE_PPE_CAP4_IDX 4
+#define HE_PPE_CAP4_PPET16_FOR_NSS2_FOR_RU0 ((u8) (BIT(0) | BIT(1)))
+#define HE_PPE_CAP4_PPET8_FOR_NSS2_FOR_RU0 ((u8) (BIT(2) | BIT(3) | BIT(4)))
+#define HE_PPE_CAP4_PPET16_FOR_NSS2_FOR_RU1 ((u8) (BIT(5) | BIT(6) | BIT(7)))
+
+#define HE_PPE_CAP5_IDX 5
+#define HE_PPE_CAP5_PPET8_FOR_NSS2_FOR_RU1 ((u8) (BIT(0) | BIT(1) | BIT(2)))
+#define HE_PPE_CAP5_PPET16_FOR_NSS2_FOR_RU2 ((u8) (BIT(3) | BIT(4) | BIT(5)))
+#define HE_PPE_CAP5_PPET8_FOR_NSS2_FOR_RU2 ((u8) (BIT(6) | BIT(7)))
+
+#define HE_PPE_CAP6_IDX 6
+#define HE_PPE_CAP6_PPET8_FOR_NSS2_FOR_RU2 ((u8) BIT(0))
+#define HE_PPE_CAP6_PPET16_FOR_NSS2_FOR_RU3 ((u8) (BIT(1) | BIT(2) | BIT(3)))
+#define HE_PPE_CAP6_PPET8_FOR_NSS2_FOR_RU3 ((u8) (BIT(4) | BIT(5) | BIT(6)))
+#define HE_PPE_CAP6_PPET16_FOR_NSS3_FOR_RU0 ((u8) BIT(7))
+
+#define HE_PPE_CAP7_IDX 7
+#define HE_PPE_CAP7_PPET16_FOR_NSS3_FOR_RU0 ((u8) (BIT(0) | BIT(1)))
+#define HE_PPE_CAP7_PPET8_FOR_NSS3_FOR_RU0 ((u8) (BIT(2) | BIT(3) | BIT(4)))
+#define HE_PPE_CAP7_PPET16_FOR_NSS3_FOR_RU1 ((u8) (BIT(5) | BIT(6) | BIT(7)))
+
+#define HE_PPE_CAP8_IDX 8
+#define HE_PPE_CAP8_PPET8_FOR_NSS3_FOR_RU1 ((u8) (BIT(0) | BIT(1) | BIT(2)))
+#define HE_PPE_CAP8_PPET16_FOR_NSS3_FOR_RU2 ((u8) (BIT(3) | BIT(4) | BIT(5)))
+#define HE_PPE_CAP8_PPET8_FOR_NSS3_FOR_RU2 ((u8) (BIT(6) | BIT(7)))
+
+#define HE_PPE_CAP9_IDX 9
+#define HE_PPE_CAP9_PPET8_FOR_NSS3_FOR_RU2 ((u8) BIT(0))
+#define HE_PPE_CAP9_PPET16_FOR_NSS3_FOR_RU3 ((u8) (BIT(1) | BIT(2) | BIT(3)))
+#define HE_PPE_CAP9_PPET8_FOR_NSS3_FOR_RU3 ((u8) (BIT(4) | BIT(5) | BIT(6)))
+#define HE_PPE_CAP9_PPET16_FOR_NSS4_FOR_RU0 ((u8) BIT(7))
+
+#define HE_PPE_CAP10_IDX 10
+#define HE_PPE_CAP10_PPET16_FOR_NSS4_FOR_RU0 ((u8) (BIT(0) | BIT(1)))
+#define HE_PPE_CAP10_PPET8_FOR_NSS4_FOR_RU0 ((u8) (BIT(2) | BIT(3) | BIT(4)))
+#define HE_PPE_CAP10_PPET16_FOR_NSS4_FOR_RU1 ((u8) (BIT(5) | BIT(6) | BIT(7)))
+
+#define HE_PPE_CAP11_IDX 11
+#define HE_PPE_CAP11_PPET8_FOR_NSS4_FOR_RU1 ((u8) (BIT(0) | BIT(1) | BIT(2)))
+#define HE_PPE_CAP11_PPET16_FOR_NSS4_FOR_RU2 ((u8) (BIT(3) | BIT(4) | BIT(5)))
+#define HE_PPE_CAP11_PPET8_FOR_NSS4_FOR_RU2 ((u8) (BIT(6) | BIT(7)))
+
+#define HE_PPE_CAP12_IDX 12
+#define HE_PPE_CAP12_PPET8_FOR_NSS4_FOR_RU2 ((u8) BIT(0))
+#define HE_PPE_CAP12_PPET16_FOR_NSS4_FOR_RU3 ((u8) (BIT(1) | BIT(2) | BIT(3)))
+#define HE_PPE_CAP12_PPET8_FOR_NSS4_FOR_RU3 ((u8) (BIT(4) | BIT(5) | BIT(6)))
+/* B7: PPE PAD */
 
 /* HE Operation defines */
 /* HE Operation Parameters and BSS Color Information fields */
