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IronPort-SDR: ICtuTWBkGstEppUeoue58OAZ2V2Y5PgcaM76aJaMDnemv/t78dqXdjQpQo7aKLiZTBZYHnson7 rAFI4HBSYVv9O4NqJUH/Al/qsUvVhvSQ0VPUI8QVjK6sRp78hwPqCHjmhr+bnpgKVS1z0yKg5e 6mI1XSFnH5wUe/GYbZiiMibG96yjkN7CjwwBDtMqEo3/4Hxe3EE1guNs2iO4D2Rio82dFGN26c 03HWimCsNVyjlEjbsMGFzG+TDR/Hj9rkIgB1oGIgBOZnXxENuQT401dBUPl6dPIQc7ous+Hsga zbR2rT/1tunJzFHq2lyTHGKp IronPort-SDR: pUDsS/JmYbmPpeZBOPZYDNwWMWwP8lEgEmKEO9h0t6lBWOCS9u7Br+b3YW1lSRQB8KDUJl3ibj 8gtPbZe1lKRHeLlPktOxgE2kZRe4Z0fgx3vD1bhAzSjHT/skDNIrRE9puDb8BQyD3xnLs12+ei uLfS1wUEZ+xc+PfXFH4gnEMneF/1CtfL+iTg0xXiAIxpdiWARjRPbjIsZdZKqWA6SwLmZ9T3Z4 R/mx/z2MH2CZYM3vaSSxNXUIzt/LlvyQQT/RJLRWH9ELA7xajWBXheS9IdhGq9He/SGN5PreG+ A7U= From: Alistair Francis To: libc-alpha@sourceware.org Cc: arnd@arndb.de, adhemerval.zanella@linaro.org, fweimer@redhat.com, palmer@sifive.com, macro@wdc.com, zongbox@gmail.com, zong@andestech.com, alistair.francis@wdc.com, alistair23@gmail.com Subject: [RFC v2 20/20] Add RISC-V 32-bit target to build-many-glibcs.py Date: Mon, 24 Jun 2019 17:09:44 -0700 Message-Id: In-Reply-To: References: MIME-Version: 1.0 From: Zong Li Support building three variant of 32 bit RISC-V glibc as follows: - riscv32-linux-gnu-rv32imac-ilp32 - riscv32-linux-gnu-rv32imafdc-ilp32 - riscv32-linux-gnu-rv32imafdc-ilp32d 2018-11-29 Zong Li * scripts/build-many-glibcs.py (Context): Add rv32 targets. --- ChangeLog | 11 +++++++++++ scripts/build-many-glibcs.py | 15 +++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/ChangeLog b/ChangeLog index f731e94fc9..b18e9730bc 100644 --- a/ChangeLog +++ b/ChangeLog @@ -101,6 +101,17 @@ * sysdeps/unix/sysv/linux/riscv/shlib-versions: Likewise. * sysdeps/riscv/preconfigure: Likewise. * sysdeps/riscv/rv32/fix-fp-int-convert-overflow.h: New file. + * sysdeps/riscv/rv32/Implies-after: New file. + * sysdeps/riscv/rv32/rvd/Implies: Likewise. + * sysdeps/riscv/rv32/rvf/Implies: Likewise. + * sysdeps/unix/sysv/linux/riscv/rv32/Implies: Likewise. + * sysdeps/unix/sysv/linux/riscv/Makefile: Support rv32. + * sysdeps/unix/sysv/linux/riscv/configure: Likewise. + * sysdeps/unix/sysv/linux/riscv/configure.ac: Likewise. + * sysdeps/unix/sysv/linux/riscv/shlib-versions: Likewise. + * sysdeps/riscv/preconfigure: Likewise. + * sysdeps/riscv/rv32/fix-fp-int-convert-overflow.h: New file. + * scripts/build-many-glibcs.py (Context): Add rv32 targets. 2019-06-20 Dmitry V. Levin Florian Weimer diff --git a/scripts/build-many-glibcs.py b/scripts/build-many-glibcs.py index c5821df25e..5923371149 100755 --- a/scripts/build-many-glibcs.py +++ b/scripts/build-many-glibcs.py @@ -318,6 +318,21 @@ class Context(object): self.add_config(arch='powerpc64le', os_name='linux-gnu', gcc_cfg=['--disable-multilib', '--enable-secureplt']) + self.add_config(arch='riscv32', + os_name='linux-gnu', + variant='rv32imac-ilp32', + gcc_cfg=['--with-arch=rv32imac', '--with-abi=ilp32', + '--disable-multilib']) + self.add_config(arch='riscv32', + os_name='linux-gnu', + variant='rv32imafdc-ilp32', + gcc_cfg=['--with-arch=rv32imafdc', '--with-abi=ilp32', + '--disable-multilib']) + self.add_config(arch='riscv32', + os_name='linux-gnu', + variant='rv32imafdc-ilp32d', + gcc_cfg=['--with-arch=rv32imafdc', '--with-abi=ilp32d', + '--disable-multilib']) self.add_config(arch='riscv64', os_name='linux-gnu', variant='rv64imac-lp64',