From patchwork Mon Mar 16 17:41:28 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Sebor X-Patchwork-Id: 450701 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id A44BB140083 for ; Tue, 17 Mar 2015 04:41:39 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass reason="1024-bit key; unprotected key" header.d=sourceware.org header.i=@sourceware.org header.b=JzRmLrG9; dkim-adsp=none (unprotected policy); dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:message-id:date:from:mime-version:to:subject :content-type; q=dns; s=default; b=qxybaIkyN4l71zqamwpjNQ7Ood/ev 8FFwcHHkIl5zw9exoQT0zNfw28D9dEgTQ3EfovQhLFiO2HKGPIeb0GjzfFEyjxAW 6OQJY5w+NhUeupKRQbR84UhypkbhDd9miqk7UDOGIcNHPZ3iXJiDPyy16Qpg554y Pgy7tvvNgPwcGA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:message-id:date:from:mime-version:to:subject :content-type; s=default; bh=9MWNphzO2dd38AVxwBTGPSDSXw8=; b=JzR mLrG9EI4EYhN2GuQDjQoCpd2FbCP7VnUTWlPk1YFZMil/DCr3tHPoBAmIf0lf4GO vdHD2H5OdrC+SXgw9J6ouOQj+BnsSA0m9hBJ3V5lrGvDzFHY7ajaZeFQaPbNyrjl Zw3sVAaXUd1YCVNSUKGcGbQ8i6e6BLawI5HfXelY= Received: (qmail 4580 invoked by alias); 16 Mar 2015 17:41:33 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 4568 invoked by uid 89); 16 Mar 2015 17:41:32 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, SPF_HELO_PASS, SPF_PASS, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: mx1.redhat.com Message-ID: <550715C8.7020508@redhat.com> Date: Mon, 16 Mar 2015 11:41:28 -0600 From: Martin Sebor User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.4.0 MIME-Version: 1.0 To: GNU C Library Subject: [PATCH] fix BZ 18116 - build failure on ppc64le: setcontext.S uses power6 mtfsf when not supported The attached patch fixes a glibc build failure with gcc 5 on powerpc64le caused by a recent change in gcc where the compiler defines the _ARCH_PWR6 macro when processing assembly files but doesn't invoke the assembler in the corresponding machine mode (unless it has been explicitly configured to target POWER 6 or later). A bug had been filed with gcc for this (65341) but was closed as won't fix. Glibc relies on the _ARCH_PWR6 macro in a few .S files to make use of Power ISA 2.5 instructions (specifically, the four-argument form of the mtfsf insn). A similar problem had occurred in the past (bug 10118) but the fix that was committed for it didn't anticipate this new problem. The fix in the proposed patch introduces the .machine "power6" directive unconditionaly, regardless of whether _ARCH_PWR6 is defined. Martin 2015-03-11 Martin Sebor * sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S (__setcontext): Set machine to power6 regardless of whether or not _ARCH_PWR6 is defined. * sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S (__novec_swapcontext): Likewise. diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S b/sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S index e47a57a..a1ed419 100644 --- a/sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S +++ b/sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S @@ -79,12 +79,13 @@ ENTRY(__novec_setcontext) lfd fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31) lfd fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31) + .machine push + .machine "power6" + # ifdef _ARCH_PWR6 /* Use the extended four-operand version of the mtfsf insn. */ mtfsf 0xff,fp0,1,0 # else - .machine push - .machine "power6" /* Availability of DFP indicates a 64-bit FPSCR. */ andi. r6,r5,PPC_FEATURE_HAS_DFP beq 5f @@ -95,8 +96,10 @@ ENTRY(__novec_setcontext) 5: mtfsf 0xff,fp0 6: - .machine pop # endif /* _ARCH_PWR6 */ + + .machine pop + lfd fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31) lfd fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31) lfd fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31) @@ -362,12 +365,13 @@ L(has_no_vec): lfd fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31) lfd fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31) + .machine push + .machine "power6" + # ifdef _ARCH_PWR6 /* Use the extended four-operand version of the mtfsf insn. */ mtfsf 0xff,fp0,1,0 # else - .machine push - .machine "power6" /* Availability of DFP indicates a 64-bit FPSCR. */ andi. r6,r5,PPC_FEATURE_HAS_DFP beq 7f @@ -378,8 +382,10 @@ L(has_no_vec): 7: mtfsf 0xff,fp0 8: - .machine pop # endif /* _ARCH_PWR6 */ + + .machine pop + lfd fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31) lfd fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31) lfd fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31) diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S b/sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S index bc02a21..b25904d 100644 --- a/sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S +++ b/sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S @@ -173,6 +173,10 @@ ENTRY(__novec_swapcontext) lfd fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31) lfd fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31) lfd fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31) + + .machine push + .machine "power6" + # ifdef _ARCH_PWR6 /* Use the extended four-operand version of the mtfsf insn. */ mtfsf 0xff,fp0,1,0 @@ -189,8 +193,10 @@ ENTRY(__novec_swapcontext) 5: mtfsf 0xff,fp0 6: - .machine pop #endif /* _ARCH_PWR6 */ + + .machine pop + lfd fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31) lfd fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31) lfd fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31) @@ -652,12 +658,14 @@ L(has_no_vec2): lfd fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31) lfd fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31) lfd fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31) + + .machine push + .machine "power6" + # ifdef _ARCH_PWR6 /* Use the extended four-operand version of the mtfsf insn. */ mtfsf 0xff,fp0,1,0 # else - .machine push - .machine "power6" /* Availability of DFP indicates a 64-bit FPSCR. */ andi. r6,r8,PPC_FEATURE_HAS_DFP beq 7f @@ -668,8 +676,10 @@ L(has_no_vec2): 7: mtfsf 0xff,fp0 8: - .machine pop #endif /* _ARCH_PWR6 */ + + .machine pop + lfd fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31) lfd fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31) lfd fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)