From patchwork Mon Nov 23 15:42:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Earnshaw X-Patchwork-Id: 1404890 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=libc-alpha-bounces@sourceware.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=sourceware.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.a=rsa-sha256 header.s=default header.b=N/YmM/4o; dkim-atps=neutral Received: from sourceware.org (unknown [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CfryZ5Lscz9sRK for ; Tue, 24 Nov 2020 02:43:02 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B81B9386F822; Mon, 23 Nov 2020 15:42:58 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B81B9386F822 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1606146178; bh=33xB7d/YwiO1DdVZZZJE2ohK2Wfe38XoUkzukfPmjRE=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=N/YmM/4o/5N472x5axPNhFG1FBKMq5JTMm5NRYQsjuJYk7ZxyzSDHettcJ9WSX4Qf g/Y4B+LydGSbnCBYwPLf2537kwMVYFIGhUBjbKvHFv8PdUYrLtpACQUyRVw6QjtJ6D YOEwSm8yyhNJoHVyJr6DMLImPvrjlGKbEdPykOGw= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 20A9C386F81C for ; Mon, 23 Nov 2020 15:42:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 20A9C386F81C Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B59DE1478; Mon, 23 Nov 2020 07:42:54 -0800 (PST) Received: from eagle.buzzard.freeserve.co.uk (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0A42C3F718; Mon, 23 Nov 2020 07:42:53 -0800 (PST) To: libc-alpha@sourceware.org Subject: [PATCH v3 2/8] elf: Add a tunable to control use of tagged memory Date: Mon, 23 Nov 2020 15:42:30 +0000 Message-Id: <20201123154236.25809-3-rearnsha@arm.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201123154236.25809-1-rearnsha@arm.com> References: <20201123154236.25809-1-rearnsha@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Earnshaw via Libc-alpha From: Richard Earnshaw Reply-To: Richard Earnshaw Cc: Richard Earnshaw Errors-To: libc-alpha-bounces@sourceware.org Sender: "Libc-alpha" Add a new glibc tunable: mtag.enable, bound to the environment variable _MTAG_ENABLE. This is a decimal constant in the range 0-255 but used as a bit-field. Bit 0 enables use of tagged memory in the malloc family of functions. Bit 1 enables precise faulting of tag failure on platforms where this can be controlled. Other bits are currently unused, but if set will cause memory tag checking for the current process to be enabled in the kernel. Reviewed-by: Siddhesh Poyarekar --- elf/dl-tunables.list | 9 +++++++++ manual/tunables.texi | 31 +++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/elf/dl-tunables.list b/elf/dl-tunables.list index e1d8225128..652cadc334 100644 --- a/elf/dl-tunables.list +++ b/elf/dl-tunables.list @@ -141,4 +141,13 @@ glibc { default: 512 } } + +memtag { + enable { + type: INT_32 + minval: 0 + maxval: 255 + env_alias: _MTAG_ENABLE + } + } } diff --git a/manual/tunables.texi b/manual/tunables.texi index d72d7a5ec0..6ab432a73f 100644 --- a/manual/tunables.texi +++ b/manual/tunables.texi @@ -36,6 +36,8 @@ their own namespace. * POSIX Thread Tunables:: Tunables in the POSIX thread subsystem * Hardware Capability Tunables:: Tunables that modify the hardware capabilities seen by @theglibc{} +* Memory Tagging Tunables:: Tunables that control the use of hardware + memory tagging @end menu @node Tunable names @@ -484,3 +486,32 @@ instead. This tunable is specific to i386 and x86-64. @end deftp + +@node Memory Tagging Tunables +@section Memory Tagging Tunables +@cindex memory tagging tunables + +@deftp {Tunable namespace} glibc.memtag +If the hardware supports memory tagging, these tunables can be used to +control the way @theglibc{} uses this feature. Currently, only AArch64 +supports this feature. +@end deftp + +@deftp Tunable glibc.memtag.enable +This tunable takes a value between 0 and 255 and acts as a bitmask +that enables various capabilities. + +Bit 0 (the least significant bit) causes the malloc subsystem to allocate +tagged memory, with each allocation being assigned a random tag. + +Bit 1 enables precise faulting mode for tag violations on systems that +support deferred tag violation reporting. This may cause programs +to run more slowly. + +Other bits are currently reserved. + +@Theglibc{} startup code will automatically enable memory tagging +support in the kernel if this tunable has any non-zero value. + +The default value is @samp{0}, which disables all memory tagging. +@end deftp