From patchwork Sat Jan 13 10:38:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 860318 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=sourceware.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=libc-alpha-return-89180-incoming=patchwork.ozlabs.org@sourceware.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.b="HQtKsowO"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zJbjc1Rz9z9sBW for ; Sat, 13 Jan 2018 21:40:19 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:subject:date:message-id:in-reply-to:references :cc:from:to; q=dns; s=default; b=uX4kl1VL9U9FZuRPyewFNIEOf9chduu ZGa4+sUJXjYivnPD/BXVU71CUpGikEO/FA6oCYsBy0dAdZAObGBw+HMlHc3Zzlli CmBw5xQnOs2JNxE9SW/x91Sg75Ee6+TdLE040rnZI4cfNO/R37cG1QHWCDZmN3wF 8us/b/QvSehg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:subject:date:message-id:in-reply-to:references :cc:from:to; s=default; bh=IGdmJmllUXcLOig1If/5rivS43Q=; b=HQtKs owOdy1vR3nn4y0TberrdN8GBFzoQl6GA0s+wjV6Od6kUaI9rn6oaSAo9f9paIy2B TNCSoNv45tlzCNyAo5jr9KGUx85ai4Rn8Yfr8wwZNLaT7ESRYylNljP/uMDIAH0Z EEgnBquhQxer2qcOpxSE+dMqiuiusMOPmGolSs= Received: (qmail 99824 invoked by alias); 13 Jan 2018 10:39:03 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 99715 invoked by uid 89); 13 Jan 2018 10:39:02 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=H*RU:209.85.160.67, Hx-spam-relays-external:209.85.160.67, 1194 X-HELO: mail-pl0-f67.google.com X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :cc:from:to; bh=RMxUn1F+wod3qaQlXQFGKRQM74lrkL+r6GJP+P0kA34=; b=lc/GaxnbvfJePEGWo/CEvGl27JcDHk/OditMu4n9JN7TnN5EwGqOvADJRIEqCmP/Rv DQJC/I65AMoaX4EpAwdHwPz3fOQNwZGYo15DnO5e/u5vgrwWxCpEPrmCkbjO/fqbjzlN 70zERk30HTvi6iYhGfLjQ5yLnnvthByUxrdZwsHmfYyrxA0eMP8XX2r5gsisuS7sm9yZ CxHJ/iczgEgqdgZAZkRHwyCn/K2rje4sWvp+azKm/emYWLI7WUPkv42G75kCVcHwgnsV mYGWmjI6u5gCy6djU75IKfm73yQmuBib78f6EtHE5Tltyn7hyRLKyHmSnW8aF3W3D03x gGtQ== X-Gm-Message-State: AKGB3mIiFeL4XbjdtBKDsnWAE4tBJwXRX+hhNVeytPR+zJPihMA4/Okd 2dLFF3XheHn6vdg5K/Uy2GcWEWkrtmk= X-Google-Smtp-Source: ACJfBov+azvJkD5CE63WwjZINb8q9+qdDQx6uwWLr9Va1Y0sQPIuu5wxE6N6Ze6RGR99WAVjA3CN0g== X-Received: by 10.84.160.194 with SMTP id v2mr29620105plg.270.1515839937173; Sat, 13 Jan 2018 02:38:57 -0800 (PST) Subject: [PATCH v4 11/17] RISC-V: Atomic and Locking Routines Date: Sat, 13 Jan 2018 02:38:10 -0800 Message-Id: <20180113103816.4861-12-palmer@dabbelt.com> In-Reply-To: <20180113103816.4861-1-palmer@dabbelt.com> References: <20180113103816.4861-1-palmer@dabbelt.com> Cc: patches@groups.riscv.org, Palmer Dabbelt From: Palmer Dabbelt To: libc-alpha@sourceware.org This patch implements various atomic and locking routines on RISC-V. We mandate the A extension on Linux-capable RISC-V systems, so this can rely on always having the various atomic instructions availiable. --- sysdeps/riscv/nptl/bits/pthreadtypes-arch.h | 76 ++++++++++ sysdeps/riscv/nptl/bits/semaphore.h | 33 +++++ sysdeps/riscv/nptl/libc-lowlevellock.c | 8 + sysdeps/unix/sysv/linux/riscv/atomic-machine.h | 194 +++++++++++++++++++++++++ 4 files changed, 311 insertions(+) create mode 100644 sysdeps/riscv/nptl/bits/pthreadtypes-arch.h create mode 100644 sysdeps/riscv/nptl/bits/semaphore.h create mode 100644 sysdeps/riscv/nptl/libc-lowlevellock.c create mode 100644 sysdeps/unix/sysv/linux/riscv/atomic-machine.h diff --git a/sysdeps/riscv/nptl/bits/pthreadtypes-arch.h b/sysdeps/riscv/nptl/bits/pthreadtypes-arch.h new file mode 100644 index 000000000000..3642ff644979 --- /dev/null +++ b/sysdeps/riscv/nptl/bits/pthreadtypes-arch.h @@ -0,0 +1,76 @@ +/* Machine-specific pthread type layouts. RISC-V version. + Copyright (C) 2011-2018 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library. If not, see + . */ + +#ifndef _BITS_PTHREADTYPES_ARCH_H +#define _BITS_PTHREADTYPES_ARCH_H 1 + +#include + +#if __riscv_xlen == 64 +# define __SIZEOF_PTHREAD_ATTR_T 56 +# define __SIZEOF_PTHREAD_MUTEX_T 40 +# define __SIZEOF_PTHREAD_MUTEXATTR_T 4 +# define __SIZEOF_PTHREAD_COND_T 48 +# define __SIZEOF_PTHREAD_CONDATTR_T 4 +# define __SIZEOF_PTHREAD_RWLOCK_T 56 +# define __SIZEOF_PTHREAD_RWLOCKATTR_T 8 +# define __SIZEOF_PTHREAD_BARRIER_T 32 +# define __SIZEOF_PTHREAD_BARRIERATTR_T 4 +#else +# define __SIZEOF_PTHREAD_ATTR_T 32 +# define __SIZEOF_PTHREAD_MUTEX_T 32 +# define __SIZEOF_PTHREAD_MUTEXATTR_T 4 +# define __SIZEOF_PTHREAD_COND_T 48 +# define __SIZEOF_PTHREAD_CONDATTR_T 4 +# define __SIZEOF_PTHREAD_RWLOCK_T 48 +# define __SIZEOF_PTHREAD_RWLOCKATTR_T 8 +# define __SIZEOF_PTHREAD_BARRIER_T 20 +# define __SIZEOF_PTHREAD_BARRIERATTR_T 4 +#endif + +#define __PTHREAD_COMPAT_PADDING_MID +#define __PTHREAD_COMPAT_PADDING_END +#define __PTHREAD_MUTEX_LOCK_ELISION 0 +#define __PTHREAD_MUTEX_USE_UNION 0 +#define __PTHREAD_MUTEX_NUSERS_AFTER_KIND 0 + +#define __LOCK_ALIGNMENT +#define __ONCE_ALIGNMENT + +/* There is a lot of padding in this structure. While it's not strictly + necessary on RISC-V, we're going to leave it in to be on the safe side in + case it's needed in the future. Most other architectures have the padding, + so this gives us the same extensibility as everyone else has. */ +struct __pthread_rwlock_arch_t +{ + unsigned int __readers; + unsigned int __writers; + unsigned int __wrphase_futex; + unsigned int __writers_futex; + unsigned int __pad3; + unsigned int __pad4; + int __cur_writer; + int __shared; + unsigned long int __pad1; + unsigned long int __pad2; + unsigned int __flags; +}; + +#define __PTHREAD_RWLOCK_ELISION_EXTRA 0 + +#endif /* bits/pthreadtypes.h */ diff --git a/sysdeps/riscv/nptl/bits/semaphore.h b/sysdeps/riscv/nptl/bits/semaphore.h new file mode 100644 index 000000000000..2fed17d0e530 --- /dev/null +++ b/sysdeps/riscv/nptl/bits/semaphore.h @@ -0,0 +1,33 @@ +/* Machine-specific POSIX semaphore type layouts. RISC-V version. + Copyright (C) 2002-2018 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library. If not, see + . */ + +#ifndef _SEMAPHORE_H +# error "Never use directly; include instead." +#endif + +#define __SIZEOF_SEM_T (4 * __SIZEOF_POINTER__) + +/* Value returned if `sem_open' failed. */ +#define SEM_FAILED ((sem_t *) 0) + + +typedef union +{ + char __size[__SIZEOF_SEM_T]; + long int __align; +} sem_t; diff --git a/sysdeps/riscv/nptl/libc-lowlevellock.c b/sysdeps/riscv/nptl/libc-lowlevellock.c new file mode 100644 index 000000000000..0ecd41e630f3 --- /dev/null +++ b/sysdeps/riscv/nptl/libc-lowlevellock.c @@ -0,0 +1,8 @@ +/* This kludge works around a libpthread static linking problem: + https://sourceware.org/bugzilla/show_bug.cgi?id=15648 */ + +#ifndef SHARED +# define __lll_lock_wait_private weak_function __lll_lock_wait_private +#endif + +#include diff --git a/sysdeps/unix/sysv/linux/riscv/atomic-machine.h b/sysdeps/unix/sysv/linux/riscv/atomic-machine.h new file mode 100644 index 000000000000..a79b7d123102 --- /dev/null +++ b/sysdeps/unix/sysv/linux/riscv/atomic-machine.h @@ -0,0 +1,194 @@ +/* Low-level functions for atomic operations. RISC-V version. + Copyright (C) 2014-2018 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library. If not, see + . */ + +#ifndef _LINUX_RISCV_BITS_ATOMIC_H +#define _LINUX_RISCV_BITS_ATOMIC_H 1 + +#include + +typedef int32_t atomic32_t; +typedef uint32_t uatomic32_t; + +typedef int64_t atomic64_t; +typedef uint64_t uatomic64_t; + +typedef intptr_t atomicptr_t; +typedef uintptr_t uatomicptr_t; +typedef intmax_t atomic_max_t; +typedef uintmax_t uatomic_max_t; + +#define atomic_full_barrier() __sync_synchronize () + +#ifdef __riscv_atomic + +# define __HAVE_64B_ATOMICS (__riscv_xlen >= 64) +# define USE_ATOMIC_COMPILER_BUILTINS 1 +# define ATOMIC_EXCHANGE_USES_CAS 0 + +/* Compare and exchange. + For all "bool" routines, we return FALSE if exchange succesful. */ + +# define __arch_compare_and_exchange_bool_8_int(mem, newval, oldval, model) \ + ({ \ + typeof (*mem) __oldval = (oldval); \ + !__atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0, \ + model, __ATOMIC_RELAXED); \ + }) + +# define __arch_compare_and_exchange_bool_16_int(mem, newval, oldval, model) \ + ({ \ + typeof (*mem) __oldval = (oldval); \ + !__atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0, \ + model, __ATOMIC_RELAXED); \ + }) + +# define __arch_compare_and_exchange_bool_32_int(mem, newval, oldval, model) \ + ({ \ + typeof (*mem) __oldval = (oldval); \ + !__atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0, \ + model, __ATOMIC_RELAXED); \ + }) + +# define __arch_compare_and_exchange_bool_64_int(mem, newval, oldval, model) \ + ({ \ + typeof (*mem) __oldval = (oldval); \ + !__atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0, \ + model, __ATOMIC_RELAXED); \ + }) + +# define __arch_compare_and_exchange_val_8_int(mem, newval, oldval, model) \ + ({ \ + typeof (*mem) __oldval = (oldval); \ + __atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0, \ + model, __ATOMIC_RELAXED); \ + __oldval; \ + }) + +# define __arch_compare_and_exchange_val_16_int(mem, newval, oldval, model) \ + ({ \ + typeof (*mem) __oldval = (oldval); \ + __atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0, \ + model, __ATOMIC_RELAXED); \ + __oldval; \ + }) + +# define __arch_compare_and_exchange_val_32_int(mem, newval, oldval, model) \ + ({ \ + typeof (*mem) __oldval = (oldval); \ + __atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0, \ + model, __ATOMIC_RELAXED); \ + __oldval; \ + }) + +# define __arch_compare_and_exchange_val_64_int(mem, newval, oldval, model) \ + ({ \ + typeof (*mem) __oldval = (oldval); \ + __atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0, \ + model, __ATOMIC_RELAXED); \ + __oldval; \ + }) + +/* Atomic compare and exchange. */ + +# define atomic_compare_and_exchange_bool_acq(mem, new, old) \ + __atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \ + mem, new, old, __ATOMIC_ACQUIRE) + +# define atomic_compare_and_exchange_val_acq(mem, new, old) \ + __atomic_val_bysize (__arch_compare_and_exchange_val, int, \ + mem, new, old, __ATOMIC_ACQUIRE) + +# define atomic_compare_and_exchange_val_rel(mem, new, old) \ + __atomic_val_bysize (__arch_compare_and_exchange_val, int, \ + mem, new, old, __ATOMIC_RELEASE) + +/* Atomic exchange (without compare). */ + +# define __arch_exchange_8_int(mem, newval, model) \ + __atomic_exchange_n (mem, newval, model) + +# define __arch_exchange_16_int(mem, newval, model) \ + __atomic_exchange_n (mem, newval, model) + +# define __arch_exchange_32_int(mem, newval, model) \ + __atomic_exchange_n (mem, newval, model) + +# define __arch_exchange_64_int(mem, newval, model) \ + __atomic_exchange_n (mem, newval, model) + +# define atomic_exchange_acq(mem, value) \ + __atomic_val_bysize (__arch_exchange, int, mem, value, __ATOMIC_ACQUIRE) + +# define atomic_exchange_rel(mem, value) \ + __atomic_val_bysize (__arch_exchange, int, mem, value, __ATOMIC_RELEASE) + +/* Atomically add value and return the previous (unincremented) value. */ + +# define __arch_exchange_and_add_8_int(mem, value, model) \ + __atomic_fetch_add (mem, value, model) + +# define __arch_exchange_and_add_16_int(mem, value, model) \ + __atomic_fetch_add (mem, value, model) + +# define __arch_exchange_and_add_32_int(mem, value, model) \ + __atomic_fetch_add (mem, value, model) + +# define __arch_exchange_and_add_64_int(mem, value, model) \ + __atomic_fetch_add (mem, value, model) + +# define atomic_exchange_and_add_acq(mem, value) \ + __atomic_val_bysize (__arch_exchange_and_add, int, mem, value, \ + __ATOMIC_ACQUIRE) + +# define atomic_exchange_and_add_rel(mem, value) \ + __atomic_val_bysize (__arch_exchange_and_add, int, mem, value, \ + __ATOMIC_RELEASE) + +/* Miscellaneous. */ + +# define asm_amo(which, ordering, mem, value) ({ \ + __atomic_check_size (mem); \ + typeof (*mem) __tmp; \ + if (sizeof (__tmp) == 4) \ + asm volatile (which ".w" ordering "\t%0, %z2, %1" \ + : "=r" (__tmp), "+A" (* (mem)) \ + : "rJ" (value)); \ + else if (sizeof (__tmp) == 8) \ + asm volatile (which ".d" ordering "\t%0, %z2, %1" \ + : "=r" (__tmp), "+A" (* (mem)) \ + : "rJ" (value)); \ + else \ + abort (); \ + __tmp; }) + +# define atomic_max(mem, value) asm_amo ("amomaxu", ".aq", mem, value) +# define atomic_min(mem, value) asm_amo ("amominu", ".aq", mem, value) + +# define atomic_bit_test_set(mem, bit) \ + ({ typeof (*mem) __mask = (typeof (*mem))1 << (bit); \ + asm_amo ("amoor", ".aq", mem, __mask) & __mask; }) + +# define catomic_exchange_and_add(mem, value) \ + atomic_exchange_and_add (mem, value) +# define catomic_max(mem, value) atomic_max (mem, value) + +#else /* __riscv_atomic */ +# error "ISAs that do not subsume the A extension are not supported" +#endif /* !__riscv_atomic */ + +#endif /* bits/atomic.h */