From patchwork Wed May 11 20:00:08 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 621248 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3r4n6B0PGqz9t0t for ; Thu, 12 May 2016 06:00:17 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.b=UBGueeVn; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:date:from:to:subject:message-id:reply-to :mime-version:content-type; q=dns; s=default; b=Y4X2jBVqOqkX4mq8 StR1mDA+xkcu7gdMcTmRWoZynhdXmYIVDemAmEkepkmUxcYWnN1RmigWFScwha+u 5dhFmlX1NZvSFZC/vPnJFJ2tS7HbtDwHcqtLpMaXIapkVyJfBeNheorC0cBOHuyp aKtxnWdJceV4Ie4jWiSSvyUj7LY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:date:from:to:subject:message-id:reply-to :mime-version:content-type; s=default; bh=6eEEEHTxkhZ3cOqmQ0T0tm uhCvg=; b=UBGueeVnWBtIAojWv/rC9wMDHzXqf1w+M9SkNrdvjH3go3hDhlNYQM FL0bn/ZCTHyW652o7m2xSB4mJZ5ggyxbeNQoaxY7zJjl4kVU85QoSOZWdAQFQAHE IsBTjUgQw1mcK4dqSTuwRietg4VIhcIYbaEwtPqas3QtFYYzAoX4Q= Received: (qmail 105384 invoked by alias); 11 May 2016 20:00:11 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 105355 invoked by uid 89); 11 May 2016 20:00:10 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.2 required=5.0 tests=AWL, BAYES_00, KAM_LAZY_DOMAIN_SECURITY, NO_DNS_FOR_FROM, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=H*R:D*gmail.com X-HELO: mga14.intel.com X-ExtLoop1: 1 Date: Wed, 11 May 2016 13:00:08 -0700 From: "H.J. Lu" To: GNU C Library Subject: [PATCH] Support non-inclusive caches on Intel processors Message-ID: <20160511200007.GA29005@intel.com> Reply-To: "H.J. Lu" MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.6.0 (2016-04-01) Tested on Intel processors with inclusive cache and non-inclusive cache. OK for master? H.J. --- * sysdeps/x86/cacheinfo.c (init_cacheinfo): Check and support non-inclusive caches on Intel processors. --- sysdeps/x86/cacheinfo.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c index 143b333..8408624 100644 --- a/sysdeps/x86/cacheinfo.c +++ b/sysdeps/x86/cacheinfo.c @@ -492,6 +492,9 @@ init_cacheinfo (void) { data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, max_cpuid); + long int core = handle_intel (_SC_LEVEL2_CACHE_SIZE, max_cpuid); + bool inclusive_cache = true; + /* Try L3 first. */ level = 3; shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, max_cpuid); @@ -500,7 +503,7 @@ init_cacheinfo (void) { /* Try L2 otherwise. */ level = 2; - shared = handle_intel (_SC_LEVEL2_CACHE_SIZE, max_cpuid); + shared = core; } /* Figure out the number of logical threads that share the @@ -526,6 +529,9 @@ init_cacheinfo (void) } while (((eax >> 5) & 0x7) != level); + /* Check if cache is inclusive of lower cache levels. */ + inclusive_cache = (edx & 0x2) != 0; + threads = (eax >> 14) & 0x3ff; /* If max_cpuid >= 11, THREADS is the maximum number of @@ -592,6 +598,10 @@ init_cacheinfo (void) threads. */ if (shared > 0 && threads > 0) shared /= threads; + + /* Account for non-inclusive L2 and L3 caches. */ + if (level == 3 && !inclusive_cache) + shared += core; } /* This spells out "AuthenticAMD". */ else if (is_amd)