From patchwork Tue Mar 31 16:26:48 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 456671 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id EDD1F14019D for ; Wed, 1 Apr 2015 03:26:57 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass reason="1024-bit key; unprotected key" header.d=sourceware.org header.i=@sourceware.org header.b=rR5qF1HT; dkim-adsp=none (unprotected policy); dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:date:from:to:subject:message-id:reply-to :mime-version:content-type; q=dns; s=default; b=wGNQOrpkHjSqaQfV Uhz+tcv/G345dbu7aNHR2ecGkA+6Ik1iz87kbnNf58286l5agYg0pLS0DJV1XcdV +eW7OUawfmThZ5LagbbA5b6HuiMW98mnddOn3oRevaWKaWjr08rcu2LWjteFkc3h Qindm4WsO390ZSf+0aKp7lSBemg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:date:from:to:subject:message-id:reply-to :mime-version:content-type; s=default; bh=PoR1BFCo6+pGTpLBgnUbxY 1tUt8=; b=rR5qF1HTfaQZ12sXnhC/vKBhlvk5ggtQBBaYnN1nVsQ+zXwY75t93s t0yFrBwsi3H8kXuisMHymIKfG/wSl5GYIVzK2VerPwI5WkOJ4w3IXmHIiu/M2aKP SigNHamsUr01YLcsLZ14wM7NSqdE77BIEuo31qcrVnzRLNEJfX3sc= Received: (qmail 78301 invoked by alias); 31 Mar 2015 16:26:51 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 78291 invoked by uid 89); 31 Mar 2015 16:26:51 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL, BAYES_00, NO_DNS_FOR_FROM, T_RP_MATCHES_RCVD autolearn=no version=3.3.2 X-HELO: mga03.intel.com X-ExtLoop1: 1 Date: Tue, 31 Mar 2015 09:26:48 -0700 From: "H.J. Lu" To: GNU C Library Subject: [PATCH] BZ #18185: Wrong processor count for L2 cache sharing on Silvermont and Knights Landing Message-ID: <20150331162648.GA26418@lucon.org> Reply-To: "H.J. Lu" MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.23 (2014-03-12) Hi, Silvermont and Knights Landing have a modular system design with two cores sharing an L2 cache. If more than 2 cores are detected to shared L2 cache, it should be adjusted for Silvermont and Knights Landing. I am planning to check it in shortly. H.J. --- [BZ #18185] * sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Limit threads sharing L2 cache to 2 for Silvermont/Knights Landing. --- sysdeps/x86_64/cacheinfo.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/sysdeps/x86_64/cacheinfo.c b/sysdeps/x86_64/cacheinfo.c index f1cbf50..b99fb9a 100644 --- a/sysdeps/x86_64/cacheinfo.c +++ b/sysdeps/x86_64/cacheinfo.c @@ -585,6 +585,10 @@ init_cacheinfo (void) __cpuid (1, eax, ebx_1, ecx, edx); #endif + unsigned int family = (eax >> 8) & 0x0f; + unsigned int model = (eax >> 4) & 0x0f; + unsigned int extended_model = (eax >> 12) & 0xf0; + #ifndef DISABLE_PREFERRED_MEMORY_INSTRUCTION /* Intel prefers SSSE3 instructions for memory/string routines if they are available. */ @@ -647,6 +651,25 @@ init_cacheinfo (void) } } threads += 1; + if (threads > 2 && level == 2 && family == 6) + { + model += extended_model; + switch (model) + { + case 0x57: + /* Knights Landing has L2 cache shared by 2 cores. */ + case 0x37: + case 0x4a: + case 0x4d: + case 0x5a: + case 0x5d: + /* Silvermont has L2 cache shared by 2 cores. */ + threads = 2; + break; + default: + break; + } + } } else {