[v2,08/18] riscv32: Add an architecture ipctypes.h

Message ID	1d5e19158693fc2a2cd9e7acf2d767c8954514f4.1591201405.git.alistair.francis@wdc.com
State	New
Headers	show Return-Path: <libc-alpha-bounces@sourceware.org> DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 34211388C02B IronPort-SDR: uq0P5McJURmqHUdzoYtKn33ZeA+wyvf4LohGG0UwbrkD1WuX5Ofaz9MAorFz2x//z3K2j7PWAN NnGD8rFthKjqaOUGu5bib6SIQO5uv8QkGEf6yxkva7clJATnbLG7bkU9fkcuZCvXQ72Zq0o3NT N7EsM0EuKvYDYCyVMrUiUHeMm5FSwYCGeD5hFTp3XVd89+X0sq1ezt/v87Xj03hjYfVlhWjSlS ADphduDGj6cnHZL5MQX8mfcK2Ty/wqzbJMveAm5T9VsnkLjcWycmdlFZjOmRWNtArKQrV2XBBj JbA= IronPort-SDR: rH0aOQJgnXHDC3EHFH+ecflhw6eFWG2nBXzX5od2TyaAZhxq/+KLHls2ts6Xf9dBBaTSiA1Uwa p2yVheKkuuzU3FAqD0i553EWiJ8Uh8D9w= IronPort-SDR: F9CVzDq38ofv4UuS9KJ++WmhnwCJFnOXpZmHF6xV+eYpfK4DM85SQKO8Zsq01/cFR8XZTBDZgj RwRUrPplM70g== WDCIronportException: Internal To: libc-alpha@sourceware.org Subject: [PATCH v2 08/18] riscv32: Add an architecture ipctypes.h Date: Wed, 3 Jun 2020 09:25:47 -0700 Message-Id: <1d5e19158693fc2a2cd9e7acf2d767c8954514f4.1591201405.git.alistair.francis@wdc.com> In-Reply-To: <cover.1591201405.git.alistair.francis@wdc.com> References: <cover.1591201405.git.alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list From: Alistair Francis via Libc-alpha <libc-alpha@sourceware.org> Reply-To: Alistair Francis <alistair.francis@wdc.com> Cc: alistair.francis@wdc.com Errors-To: libc-alpha-bounces@sourceware.org Sender: "Libc-alpha" <libc-alpha-bounces@sourceware.org>
Series	glibc port for 32-bit RISC-V (RV32) \| expand [v2,00/18] glibc port for 32-bit RISC-V (RV32) [v2,01/18] RISC-V: Use 64-bit time_t and off_t for RV32 and RV64 [v2,02/18] RISC-V: Define __NR_* as __NR_*_time64/64 for 32-bit [v2,03/18] RISC-V: Add support for 32-bit vDSO calls [v2,04/18] RISC-V: Support dynamic loader for the 32-bit [v2,05/18] RISC-V: Add path of library directories for the 32-bit [v2,06/18] RISC-V: Add arch-syscall.h for RV32 [v2,07/18] RISC-V: nptl: update default pthread-offsets.h [v2,08/18] riscv32: Add an architecture ipctypes.h [v2,09/18] RISC-V: The ABI implementation for 32-bit [v2,10/18] RISC-V: Hard float support for 32-bit [v2,11/18] RISC-V: Add ABI lists [v2,12/18] RISC-V: Add the RV32 libm-test-ulps [v2,13/18] RISC-V: Fix llrint and llround missing exceptions on RV32 [v2,14/18] RISC-V: Build Infastructure for 32-bit [v2,15/18] riscv32: Specify the arch_minimum_kernel as 5.4 [v2,16/18] RISC-V: Add rv32 path to RTLDLIST in ldd [v2,17/18] Documentation for the RISC-V 32-bit port [v2,18/18] Add RISC-V 32-bit target to build-many-glibcs.py

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1d5e19158693fc2a2cd9e7acf2d767c8954514f4.1591201405.git.alistair.francis@wdc.com

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To: libc-alpha@sourceware.org
Subject: [PATCH v2 08/18] riscv32: Add an architecture ipctypes.h
Date: Wed,  3 Jun 2020 09:25:47 -0700
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 <1d5e19158693fc2a2cd9e7acf2d767c8954514f4.1591201405.git.alistair.francis@wdc.com>
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Series

glibc port for 32-bit RISC-V (RV32) | expand

Commit Message

Alistair Francis June 3, 2020, 4:25 p.m. UTC

Add a RISC-V specific ipctypes.h file so we can define __IPC_CMD_TIME64
as 0.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 sysdeps/unix/sysv/linux/riscv/bits/ipctypes.h | 35 +++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 sysdeps/unix/sysv/linux/riscv/bits/ipctypes.h

Comments

Maciej W. Rozycki July 9, 2020, 2:46 a.m. UTC | #1

On Wed, 3 Jun 2020, Alistair Francis via Libc-alpha wrote:

> Add a RISC-V specific ipctypes.h file so we can define __IPC_CMD_TIME64
> as 0.

 I gather this has been superseded with upcoming commit 3ca7a464ef33 
("sysv: linux: Add 64-bit time_t variant for semctl"), right?

  Maciej

Adhemerval Zanella Netto July 9, 2020, 11:36 a.m. UTC | #2

On 08/07/2020 23:46, Maciej W. Rozycki wrote:
> On Wed, 3 Jun 2020, Alistair Francis via Libc-alpha wrote:
> 
>> Add a RISC-V specific ipctypes.h file so we can define __IPC_CMD_TIME64
>> as 0.
> 
>  I gather this has been superseded with upcoming commit 3ca7a464ef33 
> ("sysv: linux: Add 64-bit time_t variant for semctl"), right?
> 
>   Maciej
> 

Yes, this is not required anymore. I wrapping some tests before pushed it
upstream.

diff --git a/sysdeps/unix/sysv/linux/riscv/bits/ipctypes.h b/sysdeps/unix/sysv/linux/riscv/bits/ipctypes.h
new file mode 100644
index 0000000000..c73019bffb
--- /dev/null
+++ b/sysdeps/unix/sysv/linux/riscv/bits/ipctypes.h
@@ -0,0 +1,35 @@ 
+/* bits/ipctypes.h -- Define some types used by SysV IPC/MSG/SHM.
+   Copyright (C) 2012-2020 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <https://www.gnu.org/licenses/>.  */
+
+#ifndef _SYS_IPC_H
+# error "Never use <bits/ipctypes.h> directly; include <sys/ipc.h> instead."
+#endif
+
+#ifndef _BITS_IPCTYPES_H
+#define _BITS_IPCTYPES_H	1
+
+/* Used in `struct shmid_ds'.  */
+# if __WORDSIZE == 32
+typedef unsigned short int __ipc_pid_t;
+# else
+typedef int __ipc_pid_t;
+# endif
+
+#define __IPC_CMD_TIME64 0x0
+
+#endif /* bits/ipctypes.h */

[v2,08/18] riscv32: Add an architecture ipctypes.h

Commit Message

Comments

Patch