From patchwork Mon Mar 7 17:36:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 593085 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 6095C140216 for ; Tue, 8 Mar 2016 04:38:27 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.b=Qg7MY4xd; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id:in-reply-to :references; q=dns; s=default; b=KiD5N7edRGWVeQq6bawJ2yHndg3jSG/ JIybjpeQVwHwe5uO96IUJPhtD9u/DM0aMnMPRWqFYk5yARvraL49tDT41dmXsvXH YErwSwfd1WpKfr6eSUcdI+JrvTBl0Xt9GqxVLydg8GGmANujB+w7tq7YhsBSMi3A /+KiqGov8XUY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id:in-reply-to :references; s=default; bh=GueZHcri16GkXWq6ASZwda1ajJ0=; b=Qg7MY 4xdyqg6yuQuGKImfO3uRN3QVS4Myo9xFl3Ju/sUCtwDJ5bJ3aRNj394IJqO0gV6D wm7RKxvbWCSVG1Wmts1EOy5gnIKYsHa0Fx5N3UJZE5iq489rHuaEhYW+mAGFWW8C Wudz6acQcjlzGguM1+drrrqpZHJvc7RULuOITE= Received: (qmail 127716 invoked by alias); 7 Mar 2016 17:37:09 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 127609 invoked by uid 89); 7 Mar 2016 17:37:08 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=1.2 required=5.0 tests=AWL, BAYES_50, FREEMAIL_FROM, SPF_SOFTFAIL autolearn=no version=3.3.2 spammy=__mempcpy_ssse3, $16, asm-syntax.h, sk:HIDDEN_ X-HELO: mga14.intel.com X-ExtLoop1: 1 From: "H.J. Lu" To: libc-alpha@sourceware.org Cc: Ondrej Bilka Subject: [PATCH 4/7] Add entry points for __mempcpy_sse2_unaligned and _chk functions Date: Mon, 7 Mar 2016 09:36:27 -0800 Message-Id: <1457372190-12196-5-git-send-email-hjl.tools@gmail.com> In-Reply-To: <1457372190-12196-1-git-send-email-hjl.tools@gmail.com> References: <1457372190-12196-1-git-send-email-hjl.tools@gmail.com> Add entry points for __mempcpy_chk_sse2_unaligned, __mempcpy_sse2_unaligned and __memcpy_chk_sse2_unaligned. [BZ #19776] * sysdeps/x86_64/multiarch/ifunc-impl-list.c (__libc_ifunc_impl_list): Test __memcpy_chk_sse2_unaligned, __mempcpy_chk_sse2_unaligned and __mempcpy_sse2_unaligned. * sysdeps/x86_64/multiarch/memcpy-sse2-unaligned.S (__mempcpy_chk_sse2_unaligned): New. (__mempcpy_sse2_unaligned): Likewise. (__memcpy_chk_sse2_unaligned): Likewise. (L(start): New label. --- sysdeps/x86_64/multiarch/ifunc-impl-list.c | 6 ++++++ sysdeps/x86_64/multiarch/memcpy-sse2-unaligned.S | 20 ++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c index 188b6d3..47ca468 100644 --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c @@ -278,6 +278,8 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, HAS_CPU_FEATURE (SSSE3), __memcpy_chk_ssse3) IFUNC_IMPL_ADD (array, i, __memcpy_chk, 1, + __memcpy_chk_sse2_unaligned) + IFUNC_IMPL_ADD (array, i, __memcpy_chk, 1, __memcpy_chk_sse2)) /* Support sysdeps/x86_64/multiarch/memcpy.S. */ @@ -314,6 +316,8 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, HAS_CPU_FEATURE (SSSE3), __mempcpy_chk_ssse3) IFUNC_IMPL_ADD (array, i, __mempcpy_chk, 1, + __mempcpy_chk_sse2_unaligned) + IFUNC_IMPL_ADD (array, i, __mempcpy_chk, 1, __mempcpy_chk_sse2)) /* Support sysdeps/x86_64/multiarch/mempcpy.S. */ @@ -330,6 +334,8 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, __mempcpy_ssse3_back) IFUNC_IMPL_ADD (array, i, mempcpy, HAS_CPU_FEATURE (SSSE3), __mempcpy_ssse3) + IFUNC_IMPL_ADD (array, i, mempcpy, 1, + __mempcpy_sse2_unaligned) IFUNC_IMPL_ADD (array, i, mempcpy, 1, __mempcpy_sse2)) /* Support sysdeps/x86_64/multiarch/strncmp.S. */ diff --git a/sysdeps/x86_64/multiarch/memcpy-sse2-unaligned.S b/sysdeps/x86_64/multiarch/memcpy-sse2-unaligned.S index 335a498..947c50f 100644 --- a/sysdeps/x86_64/multiarch/memcpy-sse2-unaligned.S +++ b/sysdeps/x86_64/multiarch/memcpy-sse2-unaligned.S @@ -22,9 +22,29 @@ #include "asm-syntax.h" +# ifdef SHARED +ENTRY (__mempcpy_chk_sse2_unaligned) + cmpq %rdx, %rcx + jb HIDDEN_JUMPTARGET (__chk_fail) +END (__mempcpy_chk_sse2_unaligned) +# endif + +ENTRY (__mempcpy_sse2_unaligned) + mov %rdi, %rax + add %rdx, %rax + jmp L(start) +END (__mempcpy_sse2_unaligned) + +# ifdef SHARED +ENTRY (__memcpy_chk_sse2_unaligned) + cmpq %rdx, %rcx + jb HIDDEN_JUMPTARGET (__chk_fail) +END (__memcpy_chk_sse2_unaligned) +# endif ENTRY(__memcpy_sse2_unaligned) movq %rdi, %rax +L(start): testq %rdx, %rdx je L(return) cmpq $16, %rdx