From patchwork Fri May 23 15:16:49 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wilco X-Patchwork-Id: 351878 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 0DCE9140078 for ; Sat, 24 May 2014 01:17:14 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id:mime-version :content-type; q=dns; s=default; b=X712cEB0oNVEyvKTmFhGO6qxeq8rv 0XptJWR6Wm4x9ko/eu/KTELtXZeuQ83S94IJ2JXeXAy+ID1MevZbqqrKplvVOzh1 TWM0BZkzomgGMmzjmTI7LlGlwr3DoCkC5jLZHnrI78oOxHt4AEGM45TeG5Irn8Jr H2iqjvZgyXwpAI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id:mime-version :content-type; s=default; bh=h+GcEr6uGDJTPmoRwOp7GaPAQtQ=; b=Ju7 NHmWZieyllIV8l1sKELfdChfksGVO5IoLVm4sHVY41Mhe3U5zSQ4ntr3BG2QRNQN itWjU4WlrMdOvX84Ckp8eKQN6J4gtz7bzquVz8RwFyOP2G8x/zGrDs2XMNpxfAWm xB3M/tQ34WMIaXmBBWFgYrz2gBsilOg+T0vUNX7s= Received: (qmail 13117 invoked by alias); 23 May 2014 15:17:02 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 13040 invoked by uid 89); 23 May 2014 15:17:01 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com From: "Wilco" To: Subject: [PATCH] Aarch64 : Remove ISB after FPCR write Date: Fri, 23 May 2014 16:16:49 +0100 Message-ID: <000d01cf769a$04fd6430$0ef82c90$@com> MIME-Version: 1.0 X-MC-Unique: 114052316165726201 Hi, This patch removes ISB after FPCR writes as it is no longer required by the architecture. OK? Wilco ChangeLog: 2014-05-23 Wilco * sysdeps/aarch64/fpu/fpu_control.h: Remove ISB after FPCR write. --- sysdeps/aarch64/fpu/fpu_control.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h index 6a265e8..d5a890d 100644 --- a/sysdeps/aarch64/fpu/fpu_control.h +++ b/sysdeps/aarch64/fpu/fpu_control.h @@ -24,11 +24,8 @@ #define _FPU_GETCW(fpcr) \ __asm__ __volatile__ ("mrs %0, fpcr" : "=r" (fpcr)) -#define _FPU_SETCW(fpcr) \ - { \ - __asm__ __volatile__ ("msr fpcr, %0" : : "r" (fpcr)); \ - __asm__ __volatile__ ("isb"); \ - } +#define _FPU_SETCW(fpcr) \ + __asm__ __volatile__ ("msr fpcr, %0" : : "r" (fpcr)) #define _FPU_GETFPSR(fpsr) \ __asm__ __volatile__ ("mrs %0, fpsr" : "=r" (fpsr))