From patchwork Wed Aug 19 15:38:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 1347898 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=libc-alpha-bounces@sourceware.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=sourceware.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.a=rsa-sha256 header.s=default header.b=E/zSS2gw; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BWsdl225hz9sRK for ; Thu, 20 Aug 2020 01:48:58 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 951DD386EC72; Wed, 19 Aug 2020 15:48:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 951DD386EC72 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1597852134; bh=UhAXTYu+dkdfuj0/s1gdDgixhhdIXY7ItgKdvA4N+UY=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=E/zSS2gw8WRvwX6teukjtbrM4RX5N/UE9f/Cipt1W6PkSiYwl1rBPz/b5WgrnzI9L 2NPP7bPD8kE4LClw4ZE2ur3oEK9bgfGywurX7M8SoEjSv56lwka7FosQ0LVOfB0juO 5woHFnQR2j6/+x+cCI/aP3Kz9Qh/B0OUKPfRxo/Q= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from esa1.hgst.iphmx.com (esa1.hgst.iphmx.com [68.232.141.245]) by sourceware.org (Postfix) with ESMTPS id 948513857C42 for ; Wed, 19 Aug 2020 15:48:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 948513857C42 IronPort-SDR: UyySMxiKJfjDnfRN+a9ioOBFDXs7pM/vwYyelW08Y+YoBwhIIDWyPBs9sUVCd2I6S2BARtca3w u3c7SXVM5HyLk9vitMwgvNdowzZP2NKI9W2l3aM9osiVuYCxOEoIQ3xhTXUZh6kPcUzD85yFEN k1AnQ1fmHBbBZDCptGcSeee1MtmhraIQKgxsGqTufr8Umtv1VO+nK3hHasYT7XM6oxG8emBudl vFlVsAyYklHdvm+JQ7EKvtn2z4wH0oRkfEyn2P8jh9iOPP4y+U5zjGKIkXkSAqGvh072+cN6FE OEY= X-IronPort-AV: E=Sophos;i="5.76,331,1592841600"; d="scan'208";a="254766915" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 19 Aug 2020 23:48:47 +0800 IronPort-SDR: plPY8e6WLc878+H5Dqpd2OIE6H67bAMiut/pyxxhEZV2PMFbm+2rJA7jVcmzwx3PYLq/6T+ULC bCXIasR6YO/Q== Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Aug 2020 08:35:45 -0700 IronPort-SDR: qsAc3CK7rItg5Urs15nZ7k7XKo5kb85Rh2kZiYzbl14Mg5+/9LcCJUeeBL6E55BuUtY9fgo+pE te5dftW1cyCA== WDCIronportException: Internal Received: from lpt-kalia-a.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.59.58]) by uls-op-cesaip01.wdc.com with ESMTP; 19 Aug 2020 08:48:47 -0700 To: libc-alpha@sourceware.org Subject: [PATCH v5 00/17] glibc port for 32-bit RISC-V (RV32) Date: Wed, 19 Aug 2020 08:38:38 -0700 Message-Id: X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Alistair Francis via Libc-alpha From: Alistair Francis Reply-To: Alistair Francis Cc: alistair.francis@wdc.com Errors-To: libc-alpha-bounces@sourceware.org Sender: "Libc-alpha" This patch set contains the glibc port for 32-bit RISC-V. This is based on the original work from Zong Li [1] and has been updated to use a 64-bit time_t. This requires a 5.4+ kernel and all of the testing has been done using the 5.4 stable kernel. Nothing fails when running ./scripts/build-many-glibcs.py (for all targets) on my x86-64 machine. This is the current list of tests that fail when running inside QEMU RV32 system emulation on the 5.4 kernel: FAIL: elf/tst-libc_dlvsym FAIL: elf/tst-libc_dlvsym-static FAIL: io/tst-lockf FAIL: stdlib/tst-strfrom FAIL: stdlib/tst-strfrom-locale ---Links--- 1: https://sourceware.org/ml/libc-alpha/2018-07/msg00892.html The latest version of my work can be found here: https://github.com/alistair23/glibc/tree/alistair/rv32.next This specific version can be found here: https://github.com/alistair23/glibc/tree/alistair/rv32.5 ---Changelog--- v5: - Small fiexes based on v4 comments v4: - Address comments on v3 v3: - Re-write the library path detection - Drop the ipctypes change - Fix comments and code sytle - Use __WORDSIZE in replace of __riscv_xlen in places - Other changes requested in review v2: - Rebase on master v1: - Update based from feedback on RFCv6 - Improve test passing - There are only 9 tests failing now - Rebase on Lukasz's work - Send only the RV32 specific patches (other patches are already merged or on the list) RFC v6: - Rebase on top of accetpted patches - Fix issues so that the tests actually run RFC v5: - Hopefully finally get the correct layout for the *64 syscalls - Sort out the Changelog RFC v4: - Continue to fix things that weren't working - Update the coding style to match glibc - Update the __ASSUME_TIME64_SYSCALLS work to better match Lukasz's work RFC v3: - Remove all "Hack" patches - Incorporate upstream comments - Ensure we don't break RV64 - Lot's more testing and fixes RFC v2: - Add Lukasz's patches - Update the non HACK syscalls after feedback - define __ASSUME_TIME64_SYSCALLS and __ASSUME_RLIM64_SYSCALLS - Remove lockf64.c - Other smaller changes from RFC v1 Alistair Francis (11): RISC-V: Use 64-bit time_t and off_t for RV32 and RV64 RISC-V: Cleanup some of the sysdep.h code RISC-V: Use 64-bit-time syscall numbers with the 32-bit port RISC-V: Add support for 32-bit vDSO calls RISC-V: Add path of library directories for the 32-bit RISC-V: Add arch-syscall.h for RV32 RISC-V: Support the 32-bit ABI implementation RISC-V: Add 32-bit ABI lists RISC-V: Add the RV32 libm-test-ulps riscv32: Specify the arch_minimum_kernel as 5.4 Documentation for the RISC-V 32-bit port Zong Li (6): RISC-V: Support dynamic loader for the 32-bit RISC-V: Add hard float support for 32-bit CPUs RISC-V: Fix llrint and llround missing exceptions on RV32 RISC-V: Add rv32 path to RTLDLIST in ldd RISC-V: Build infastructure for 32-bit port Add RISC-V 32-bit target to build-many-glibcs.py NEWS | 11 +- README | 1 + scripts/build-many-glibcs.py | 15 + sysdeps/riscv/bits/wordsize.h | 9 +- sysdeps/riscv/nptl/bits/pthreadtypes-arch.h | 26 +- sysdeps/riscv/nptl/bits/struct_rwlock.h | 27 +- sysdeps/riscv/nptl/pthread-offsets.h | 17 +- sysdeps/riscv/preconfigure | 6 +- sysdeps/riscv/rv32/Implies-after | 1 + .../riscv/rv32/fix-fp-int-convert-overflow.h | 38 + sysdeps/riscv/rv32/rvd/Implies | 3 + sysdeps/riscv/rv32/rvd/libm-test-ulps | 1405 ++++++++++++ sysdeps/riscv/rv32/rvd/libm-test-ulps-name | 1 + sysdeps/riscv/rv32/rvd/s_lrint.c | 31 + sysdeps/riscv/rv32/rvd/s_lround.c | 31 + sysdeps/riscv/rv32/rvf/Implies | 1 + sysdeps/riscv/rv32/rvf/s_lrintf.c | 31 + sysdeps/riscv/rv32/rvf/s_lroundf.c | 31 + sysdeps/riscv/sfp-machine.h | 27 +- sysdeps/riscv/sys/asm.h | 7 +- sysdeps/unix/sysv/linux/riscv/Makefile | 8 +- .../unix/sysv/linux/riscv/bits/environments.h | 81 + sysdeps/unix/sysv/linux/riscv/bits/time64.h | 36 + sysdeps/unix/sysv/linux/riscv/bits/timesize.h | 22 + sysdeps/unix/sysv/linux/riscv/configure | 43 + sysdeps/unix/sysv/linux/riscv/configure.ac | 12 + sysdeps/unix/sysv/linux/riscv/dl-cache.h | 54 +- .../unix/sysv/linux/riscv/jmp_buf-macros.h | 55 + sysdeps/unix/sysv/linux/riscv/kernel_stat.h | 23 + sysdeps/unix/sysv/linux/riscv/ldconfig.h | 2 +- sysdeps/unix/sysv/linux/riscv/ldd-rewrite.sed | 2 +- sysdeps/unix/sysv/linux/riscv/rv32/Implies | 3 + .../unix/sysv/linux/riscv/rv32/arch-syscall.h | 284 +++ .../unix/sysv/linux/riscv/rv32/c++-types.data | 67 + sysdeps/unix/sysv/linux/riscv/rv32/ld.abilist | 5 + .../linux/riscv/rv32/libBrokenLocale.abilist | 1 + .../unix/sysv/linux/riscv/rv32/libanl.abilist | 4 + .../unix/sysv/linux/riscv/rv32/libc.abilist | 1935 +++++++++++++++++ .../sysv/linux/riscv/rv32/libcrypt.abilist | 2 + .../unix/sysv/linux/riscv/rv32/libdl.abilist | 9 + .../unix/sysv/linux/riscv/rv32/libm.abilist | 940 ++++++++ .../sysv/linux/riscv/rv32/libpthread.abilist | 213 ++ .../sysv/linux/riscv/rv32/libresolv.abilist | 79 + .../unix/sysv/linux/riscv/rv32/librt.abilist | 35 + .../linux/riscv/rv32/libthread_db.abilist | 40 + .../sysv/linux/riscv/rv32/libutil.abilist | 6 + sysdeps/unix/sysv/linux/riscv/shlib-versions | 10 +- sysdeps/unix/sysv/linux/riscv/sysdep.h | 59 +- 48 files changed, 5681 insertions(+), 68 deletions(-) create mode 100644 sysdeps/riscv/rv32/Implies-after create mode 100644 sysdeps/riscv/rv32/fix-fp-int-convert-overflow.h create mode 100644 sysdeps/riscv/rv32/rvd/Implies create mode 100644 sysdeps/riscv/rv32/rvd/libm-test-ulps create mode 100644 sysdeps/riscv/rv32/rvd/libm-test-ulps-name create mode 100644 sysdeps/riscv/rv32/rvd/s_lrint.c create mode 100644 sysdeps/riscv/rv32/rvd/s_lround.c create mode 100644 sysdeps/riscv/rv32/rvf/Implies create mode 100644 sysdeps/riscv/rv32/rvf/s_lrintf.c create mode 100644 sysdeps/riscv/rv32/rvf/s_lroundf.c create mode 100644 sysdeps/unix/sysv/linux/riscv/bits/environments.h create mode 100644 sysdeps/unix/sysv/linux/riscv/bits/time64.h create mode 100644 sysdeps/unix/sysv/linux/riscv/bits/timesize.h create mode 100644 sysdeps/unix/sysv/linux/riscv/jmp_buf-macros.h create mode 100644 sysdeps/unix/sysv/linux/riscv/kernel_stat.h create mode 100644 sysdeps/unix/sysv/linux/riscv/rv32/Implies create mode 100644 sysdeps/unix/sysv/linux/riscv/rv32/arch-syscall.h create mode 100644 sysdeps/unix/sysv/linux/riscv/rv32/c++-types.data create mode 100644 sysdeps/unix/sysv/linux/riscv/rv32/ld.abilist create mode 100644 sysdeps/unix/sysv/linux/riscv/rv32/libBrokenLocale.abilist create mode 100644 sysdeps/unix/sysv/linux/riscv/rv32/libanl.abilist create mode 100644 sysdeps/unix/sysv/linux/riscv/rv32/libc.abilist create mode 100644 sysdeps/unix/sysv/linux/riscv/rv32/libcrypt.abilist create mode 100644 sysdeps/unix/sysv/linux/riscv/rv32/libdl.abilist create mode 100644 sysdeps/unix/sysv/linux/riscv/rv32/libm.abilist create mode 100644 sysdeps/unix/sysv/linux/riscv/rv32/libpthread.abilist create mode 100644 sysdeps/unix/sysv/linux/riscv/rv32/libresolv.abilist create mode 100644 sysdeps/unix/sysv/linux/riscv/rv32/librt.abilist create mode 100644 sysdeps/unix/sysv/linux/riscv/rv32/libthread_db.abilist create mode 100644 sysdeps/unix/sysv/linux/riscv/rv32/libutil.abilist