| Message ID | ri6y2dme4e7.fsf@suse.cz |
|---|---|
| State | New |
| Headers | show |
| Series | [wwwdocs] Add znver3 support to changes.html | expand |
Hi, I'd like to ping the following, since we already have an RC. Thanks, On Tue, Apr 13 2021, Martin Jambor wrote: > Hi, > > Martin Liška correctly observed that the newly added support for AMD > zenver3 in GCC 11 and 10.3 is not reflected in the changes.html files. > > Would the following be OK? > > Thanks, > > Martin > > > diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html > index d5166879..d9971ffb 100644 > --- a/htdocs/gcc-10/changes.html > +++ b/htdocs/gcc-10/changes.html > @@ -1144,6 +1144,12 @@ are not listed here).</p> > makes the code specific to 512-bit SVE.</li> > </ul> > > +<h3>x86-64</h3> > +<ul> > + <li>GCC 10.3 supports AMD CPUs based on <code>znver3</code> core > + through <code>-march=znver3</code>. > + </li> > +</ul> > <!-- .................................................................. --> > > </body> > diff --git a/htdocs/gcc-11/changes.html b/htdocs/gcc-11/changes.html > index a7fa4e1b..97a622f4 100644 > --- a/htdocs/gcc-11/changes.html > +++ b/htdocs/gcc-11/changes.html > @@ -634,6 +634,9 @@ a work-in-progress.</p> > The switch enables the CLDEMOTE, PTWRITE, WAITPKG, SERIALIZE, KEYLOCKER, > AVX-VNNI, and HRESET ISA extensions. > </li> > + <li>GCC now supports AMD CPUs based on <code>znver3</code> core > + through <code>-march=znver3</code>. > + </li> > </ul> > >
Hi Martin, On Tue, 20 Apr 2021, Martin Jambor wrote: > I'd like to ping the following, since we already have an RC. sorry for not getting to this via list right away. > > + <li>GCC 10.3 supports AMD CPUs based on <code>znver3</code> core > > + through <code>-march=znver3</code>. I believe "based on the ... core" will be better and (just a recommendation, totally your call) would use "via" over "through" to make this more direct. This applies to both parts of the original patch and both are fine. :) Thank you, Gerald
diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html index d5166879..d9971ffb 100644 --- a/htdocs/gcc-10/changes.html +++ b/htdocs/gcc-10/changes.html @@ -1144,6 +1144,12 @@ are not listed here).</p> makes the code specific to 512-bit SVE.</li> </ul> +<h3>x86-64</h3> +<ul> + <li>GCC 10.3 supports AMD CPUs based on <code>znver3</code> core + through <code>-march=znver3</code>. + </li> +</ul> <!-- .................................................................. --> </body> diff --git a/htdocs/gcc-11/changes.html b/htdocs/gcc-11/changes.html index a7fa4e1b..97a622f4 100644 --- a/htdocs/gcc-11/changes.html +++ b/htdocs/gcc-11/changes.html @@ -634,6 +634,9 @@ a work-in-progress.</p> The switch enables the CLDEMOTE, PTWRITE, WAITPKG, SERIALIZE, KEYLOCKER, AVX-VNNI, and HRESET ISA extensions. </li> + <li>GCC now supports AMD CPUs based on <code>znver3</code> core + through <code>-march=znver3</code>. + </li> </ul>