Message ID | or1qpiyx9a.fsf@lxoliva.fsfla.org |
---|---|
State | New |
Headers | show |
Series | [testsuite,riscv] skip ssa-sink-18.c | expand |
OK, thanks! On Fri, Dec 2, 2022 at 5:24 PM Alexandre Oliva via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > > On riscv64, despite being lp64, we choose two IV candidates as on arm, > which prevents some of the expected sinking. Add an xfail for it. > > Regstraped on x86_64-linux-gnu, also tested with crosses to riscv64-elf > and arm-eabi. Ok to install? > > > for gcc/testsuite/ChangeLog > > * gcc.dg/tree-ssa/ssa-sink-18.c: xfail sink2 on riscv64. > --- > gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c > index 421c78eba50f8..9ac0fc6e4de55 100644 > --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c > +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c > @@ -207,6 +207,9 @@ compute_on_bytes (uint8_t *in_data, int in_len, uint8_t *out_data, int out_len) > from bb 31 to bb 33" > When -m32, Power and X86 will sink 3 instructions, but arm ilp32 couldn't > sink due to ivopts chooses two IV candidates instead of one, which is > - expected, so this case is restricted to lp64 only so far. */ > + expected, so this case is restricted to lp64 only so far. This different > + ivopts choice affects riscv64 as well, probably because it also lacks > + base+index addressing modes, so the ip[len] address computation can't be > + made from the IV computation above. */ > > - /* { dg-final { scan-tree-dump-times "Sunk statements: 4" 1 "sink2" { target lp64 } } } */ > + /* { dg-final { scan-tree-dump-times "Sunk statements: 4" 1 "sink2" { target lp64 xfail { riscv64-*-* } } } } */ > > -- > Alexandre Oliva, happy hacker https://FSFLA.org/blogs/lxo/ > Free Software Activist GNU Toolchain Engineer > Disinformation flourishes because many people care deeply about injustice > but very few check the facts. Ask me about <https://stallmansupport.org>
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c index 421c78eba50f8..9ac0fc6e4de55 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c @@ -207,6 +207,9 @@ compute_on_bytes (uint8_t *in_data, int in_len, uint8_t *out_data, int out_len) from bb 31 to bb 33" When -m32, Power and X86 will sink 3 instructions, but arm ilp32 couldn't sink due to ivopts chooses two IV candidates instead of one, which is - expected, so this case is restricted to lp64 only so far. */ + expected, so this case is restricted to lp64 only so far. This different + ivopts choice affects riscv64 as well, probably because it also lacks + base+index addressing modes, so the ip[len] address computation can't be + made from the IV computation above. */ - /* { dg-final { scan-tree-dump-times "Sunk statements: 4" 1 "sink2" { target lp64 } } } */ + /* { dg-final { scan-tree-dump-times "Sunk statements: 4" 1 "sink2" { target lp64 xfail { riscv64-*-* } } } } */