From patchwork Fri Jul 5 08:51:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1127897 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-504450-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="HlCUTnzv"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45g7rV3jPyz9sNp for ; Fri, 5 Jul 2019 18:52:10 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=h4sKdsDy2hM1Xj+ITSDyC30Yu4zDwbHEOWA+HUbbkY2p6QjDx7kYE zr7TFvPVjyQ6G3u9CPhwPMYMpHjzc7+WWcrxQ0c9b4asOFcANfea7A4lhvXF4gVr ReMPP3A2aSg3ylamshqXTj9yqR2QzWH9FJ6Ul5a6CqL6JYf5N8dWUw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=TFV8UgEFa3Ho1cxhbLIIkp4/ckA=; b=HlCUTnzvg6vmT29xrb4o y9aMdi3XGj7A5HYjezzLJOup2/rsvoO2UvLaX2vXWJ3EN0QyzmRYuDn/qPvB9xw4 UjtGGaxwBy18MxGIz/I+q+HKFuW8Zd6j4rMqA2IKkzUDSnq++J+RM0U8ZcQ5SKgu CEiy4ixDnjNmTuTB6U1y1OM= Received: (qmail 8749 invoked by alias); 5 Jul 2019 08:52:03 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 8739 invoked by uid 89); 5 Jul 2019 08:52:03 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-8.1 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3 autolearn=ham version=3.3.1 spammy=ll, xl, tied, 91068 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 05 Jul 2019 08:52:01 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6969A2B for ; Fri, 5 Jul 2019 01:52:00 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.39]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 10E463F246 for ; Fri, 5 Jul 2019 01:51:59 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: PR91068: Fix MIPS fallout from IRA matched operand changes Date: Fri, 05 Jul 2019 09:51:58 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 PR91068 is a case in which we have (ignoring non-LRA alternatives): [(set (match_operand:SI 0 "register_operand" "=l,d?") (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d") (match_operand:SI 2 "register_operand" "d,d")) (match_operand:SI 3 "register_operand" "0,d"))) (clobber (match_scratch:SI 4 "=X,l")) (clobber (match_scratch:SI 5 "=X,&d"))] where the first alternative is one instruction but the second is two. This is very similar to the case that my recent IRA patches were supposed to help. The crucial difference is that the cheap alternative requires a single-register class while the expensive alternative uses general registers. This makes a difference when one of operand 0 or 3 can naturally be allocated to LO but the other can't. If IRA makes that allocation, both alternatives require one reload of equal cost and so the first alternative clearly wins. However, if we say that tying operands 0 and 3 saves the cost of a full move, then all other things being equal, IRA will prefer to allocate both registers to the same GPR. The registers will then naturally fit the second alternative. This has a more drastic effect in the MIPS case than it should because using the GPR alternative is much more expensive there than it appears to the RA. But that's really a separate problem and something we were able to live with before my IRA patch. What makes tying less useful here is the fact that the tied register is a single-register class. I think in those circumstances it's better not to use tied operands at all and instead use "l" for the inputs. Allocating the input to LO, and allocating the output to LO, then depend naturally on class costs. If we decide to allocate at least one of them to LO, we'll use the cheap alternative, otherwise we'll (correctly) use the expensive alternative. This effectively restores the situation before my IRA patch, but this time making the preference on the input register more explicit. I originally wrote the patterns in the early days of IRA, and certainly well before LRA. I think they were largely influened by reload rather than RA proper (see the comment above *mul_acc_si, which is all about the reload behaviour). LRA copes with the two-"l" case just fine. The patch may well cause problems for -mno-lra, but I think we should cull that option anyway. Tested on mipsisa64-elf. OK to install? Richard 2019-07-05 Richard Sandiford gcc/ PR target/91068 * config/mips/mips.md (*mul_acc_si, *mul_acc_si_r3900, *macc) (*msac, *msac_using_macc, *mul_sub_si): Use "l" for input operands instead of matching them to "l" output operands. Index: gcc/config/mips/mips.md =================================================================== --- gcc/config/mips/mips.md 2019-07-01 09:37:07.292523884 +0100 +++ gcc/config/mips/mips.md 2019-07-05 09:46:55.219455545 +0100 @@ -1749,7 +1749,7 @@ (define_insn "*mul_acc_si" [(set (match_operand:SI 0 "register_operand" "=l*?*?,l,d?") (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d") (match_operand:SI 2 "register_operand" "d,d,d")) - (match_operand:SI 3 "register_operand" "0,0,d"))) + (match_operand:SI 3 "register_operand" "l,l,d"))) (clobber (match_scratch:SI 4 "=X,X,l")) (clobber (match_scratch:SI 5 "=X,X,&d"))] "GENERATE_MADD_MSUB && !TARGET_MIPS16" @@ -1778,7 +1778,7 @@ (define_insn "*mul_acc_si_r3900" [(set (match_operand:SI 0 "register_operand" "=l*?*?,l,d*?,d?") (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d,d") (match_operand:SI 2 "register_operand" "d,d,d,d")) - (match_operand:SI 3 "register_operand" "0,0,l,d"))) + (match_operand:SI 3 "register_operand" "l,l,l,d"))) (clobber (match_scratch:SI 4 "=X,X,3,l")) (clobber (match_scratch:SI 5 "=X,X,X,&d"))] "TARGET_MIPS3900 && !TARGET_MIPS16" @@ -1822,7 +1822,7 @@ (define_insn "*macc" [(set (match_operand:SI 0 "register_operand" "=l,d") (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d") (match_operand:SI 2 "register_operand" "d,d")) - (match_operand:SI 3 "register_operand" "0,l"))) + (match_operand:SI 3 "register_operand" "l,l"))) (clobber (match_scratch:SI 4 "=X,3"))] "ISA_HAS_MACC" { @@ -1842,7 +1842,7 @@ (define_insn "*macc" (define_insn "*msac" [(set (match_operand:SI 0 "register_operand" "=l,d") - (minus:SI (match_operand:SI 1 "register_operand" "0,l") + (minus:SI (match_operand:SI 1 "register_operand" "l,l") (mult:SI (match_operand:SI 2 "register_operand" "d,d") (match_operand:SI 3 "register_operand" "d,d")))) (clobber (match_scratch:SI 4 "=X,1"))] @@ -1862,7 +1862,7 @@ (define_insn "*msac" ;; An msac-like instruction implemented using negation and a macc. (define_insn_and_split "*msac_using_macc" [(set (match_operand:SI 0 "register_operand" "=l,d") - (minus:SI (match_operand:SI 1 "register_operand" "0,l") + (minus:SI (match_operand:SI 1 "register_operand" "l,l") (mult:SI (match_operand:SI 2 "register_operand" "d,d") (match_operand:SI 3 "register_operand" "d,d")))) (clobber (match_scratch:SI 4 "=X,1")) @@ -2005,7 +2005,7 @@ (define_peephole2 ;; See the comment above *mul_add_si for details. (define_insn "*mul_sub_si" [(set (match_operand:SI 0 "register_operand" "=l*?*?,l,d?") - (minus:SI (match_operand:SI 1 "register_operand" "0,0,d") + (minus:SI (match_operand:SI 1 "register_operand" "l,l,d") (mult:SI (match_operand:SI 2 "register_operand" "d,d,d") (match_operand:SI 3 "register_operand" "d,d,d")))) (clobber (match_scratch:SI 4 "=X,X,l"))