[pushed] aarch64: Support conditional unpacked UXT on SVE

Message ID	mptpn2fem5u.fsf@arm.com
State	New
Headers	show Return-Path: <gcc-patches-bounces@gcc.gnu.org> DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 10C5D385801A To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [pushed] aarch64: Support conditional unpacked UXT on SVE Date: Fri, 08 Jan 2021 10:51:57 +0000 Message-ID: <mptpn2fem5u.fsf@arm.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain Precedence: list From: Richard Sandiford via Gcc-patches <gcc-patches@gcc.gnu.org> Reply-To: Richard Sandiford <richard.sandiford@arm.com> Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces@gcc.gnu.org>
Series	[pushed] aarch64: Support conditional unpacked UXT on SVE \| expand [pushed] aarch64: Support conditional unpacked UXT on SVE

diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 2ec9acbf38d..b83f9912cb6 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -3135,12 +3135,12 @@ (define_insn "@aarch64_cond_sxt<SVE_FULL_HSDI:mode><SVE_PARTIAL_I:mode>" ;; The canonical form of this operation is an AND of a constant rather ;; than (zero_extend (truncate ...)). (define_insn "*cond_uxt<mode>_2" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl") - (and:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand" "0, w") - (match_operand:SVE_FULL_I 3 "aarch64_sve_uxt_immediate")) + (and:SVE_I + (match_operand:SVE_I 2 "register_operand" "0, w") + (match_operand:SVE_I 3 "aarch64_sve_uxt_immediate")) (match_dup 2)] UNSPEC_SEL))] "TARGET_SVE" @@ -3159,13 +3159,13 @@ (define_insn "*cond_uxt<mode>_2" ;; as early-clobber helps to make the instruction more regular to the ;; register allocator. (define_insn "*cond_uxt<mode>_any" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=&w, ?&w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=&w, ?&w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl") - (and:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand" "w, w, w") - (match_operand:SVE_FULL_I 3 "aarch64_sve_uxt_immediate")) - (match_operand:SVE_FULL_I 4 "aarch64_simd_reg_or_zero" "0, Dz, w")] + (and:SVE_I + (match_operand:SVE_I 2 "register_operand" "w, w, w") + (match_operand:SVE_I 3 "aarch64_sve_uxt_immediate")) + (match_operand:SVE_I 4 "aarch64_simd_reg_or_zero" "0, Dz, w")] UNSPEC_SEL))] "TARGET_SVE && !rtx_equal_p (operands[2], operands[4])" "@ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_5.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_5.c new file mode 100644 index 00000000000..18866286b7f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_5.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include <stdint.h> + +#define DEF_LOOP(TYPE1, TYPE2, CONST, COUNT) \ + void __attribute__ ((noipa)) \ + test_##CONST##_##TYPE1##_##TYPE2 (TYPE2 *restrict r, \ + TYPE1 *restrict a, \ + TYPE2 *restrict b) \ + { \ + for (int i = 0; i < COUNT; ++i) \ + r[i] = a[i] > 20 ? b[i] & CONST : b[i]; \ + } + +#define TEST_ALL(T) \ + T (int32_t, uint16_t, 0xff, 3) \ + \ + T (int64_t, uint16_t, 0xff, 5) \ + T (int64_t, uint32_t, 0xff, 5) \ + T (int64_t, uint32_t, 0xffff, 5) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.s, p[0-7]/z, \[x2[],][^L]*\tuxtb\t\1\.h, p[0-7]/m, \1\.h\n} } } */ + +/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.d, p[0-7]/z, \[x2[],][^L]*\tuxtb\t\1\.h, p[0-7]/m, \1\.h\n} } } */ +/* { dg-final { scan-assembler {\tld1w\t(z[0-9]+)\.d, p[0-7]/z, \[x2[],][^L]*\tuxtb\t\1\.s, p[0-7]/m, \1\.s\n} } } */ +/* { dg-final { scan-assembler {\tld1w\t(z[0-9]+)\.d, p[0-7]/z, \[x2[],][^L]*\tuxth\t\1\.s, p[0-7]/m, \1\.s\n} } } */ + +/* { dg-final { scan-assembler-not {\tmov\tz[^\n]*z} } } */ +/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */ +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_5_run.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_5_run.c new file mode 100644 index 00000000000..675fd2be96b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_5_run.c @@ -0,0 +1,26 @@ +/* { dg-do run { target { aarch64_sve_hw } } } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_uxt_5.c" + +#define TEST_LOOP(TYPE1, TYPE2, CONST, N) \ + { \ + TYPE1 a[N]; \ + TYPE2 r[N], b[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? -20 - i : 20 + i); \ + b[i] = -5 - i; \ + asm volatile ("" ::: "memory"); \ + } \ + test_##CONST##_##TYPE1##_##TYPE2 (r, a, b); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (TYPE2) (a[i] > 20 ? b[i] & CONST : b[i])) \ + __builtin_abort (); \ + } + +int main () +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_6.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_6.c new file mode 100644 index 00000000000..e47276a3a35 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_6.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include <stdint.h> + +#define DEF_LOOP(TYPE1, TYPE2, CONST, COUNT) \ + void __attribute__ ((noipa)) \ + test_##CONST##_##TYPE1##_##TYPE2 (TYPE2 *restrict r, \ + TYPE1 *restrict a, \ + TYPE2 *restrict b) \ + { \ + for (int i = 0; i < COUNT; ++i) \ + r[i] = a[i] > 20 ? b[i] & CONST : a[i]; \ + } + +#define TEST_ALL(T) \ + T (int32_t, uint16_t, 0xff, 3) \ + \ + T (int64_t, uint16_t, 0xff, 5) \ + T (int64_t, uint32_t, 0xff, 5) \ + T (int64_t, uint32_t, 0xffff, 5) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler {\tld1w\t(z[0-9]+)\.s, p[0-7]/z, \[x1[],][^L]*\tld1h\t(z[0-9]+)\.s, p[0-7]/z, \[x2[],][^L]*\tuxtb\t\1\.h, p[0-7]/m, \2\.h\n} } } */ + +/* { dg-final { scan-assembler {\tld1d\t(z[0-9]+)\.d, p[0-7]/z, \[x1[],][^L]*\tld1h\t(z[0-9]+)\.d, p[0-7]/z, \[x2[],][^L]*\tuxtb\t\1\.h, p[0-7]/m, \2\.h\n} } } */ +/* { dg-final { scan-assembler {\tld1d\t(z[0-9]+)\.d, p[0-7]/z, \[x1[],][^L]*\tld1w\t(z[0-9]+)\.d, p[0-7]/z, \[x2[],][^L]*\tuxtb\t\1\.s, p[0-7]/m, \2\.s\n} } } */ +/* { dg-final { scan-assembler {\tld1d\t(z[0-9]+)\.d, p[0-7]/z, \[x1[],][^L]*\tld1w\t(z[0-9]+)\.d, p[0-7]/z, \[x2[],][^L]*\tuxth\t\1\.s, p[0-7]/m, \2\.s\n} } } */ + +/* { dg-final { scan-assembler-not {\tmov\tz[^\n]*z} } } */ +/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */ +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_6_run.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_6_run.c new file mode 100644 index 00000000000..72208542b88 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_6_run.c @@ -0,0 +1,26 @@ +/* { dg-do run { target { aarch64_sve_hw } } } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_uxt_6.c" + +#define TEST_LOOP(TYPE1, TYPE2, CONST, N) \ + { \ + TYPE1 a[N]; \ + TYPE2 r[N], b[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? -20 - i : 20 + i); \ + b[i] = -5 - i; \ + asm volatile ("" ::: "memory"); \ + } \ + test_##CONST##_##TYPE1##_##TYPE2 (r, a, b); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (TYPE2) (a[i] > 20 ? b[i] & CONST : a[i])) \ + __builtin_abort (); \ + } + +int main () +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_7.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_7.c new file mode 100644 index 00000000000..f49915c4ac1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_7.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include <stdint.h> + +#define DEF_LOOP(TYPE1, TYPE2, CONST, COUNT) \ + void __attribute__ ((noipa)) \ + test_##CONST##_##TYPE1##_##TYPE2 (TYPE2 *restrict r, \ + TYPE1 *restrict a, \ + TYPE2 *restrict b) \ + { \ + for (int i = 0; i < COUNT; ++i) \ + r[i] = a[i] > 20 ? b[i] & CONST : 127; \ + } + +#define TEST_ALL(T) \ + T (int32_t, uint16_t, 0xff, 3) \ + \ + T (int64_t, uint16_t, 0xff, 5) \ + T (int64_t, uint32_t, 0xff, 5) \ + T (int64_t, uint32_t, 0xffff, 5) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_7_run.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_7_run.c new file mode 100644 index 00000000000..4c6dc36583c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_7_run.c @@ -0,0 +1,26 @@ +/* { dg-do run { target { aarch64_sve_hw } } } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_uxt_7.c" + +#define TEST_LOOP(TYPE1, TYPE2, CONST, N) \ + { \ + TYPE1 a[N]; \ + TYPE2 r[N], b[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? -20 - i : 20 + i); \ + b[i] = -5 - i; \ + asm volatile ("" ::: "memory"); \ + } \ + test_##CONST##_##TYPE1##_##TYPE2 (r, a, b); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (TYPE2) (a[i] > 20 ? b[i] & CONST : 127)) \ + __builtin_abort (); \ + } + +int main () +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_8.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_8.c new file mode 100644 index 00000000000..42eb4b2661b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_8.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include <stdint.h> + +#define DEF_LOOP(TYPE1, TYPE2, CONST, COUNT) \ + void __attribute__ ((noipa)) \ + test_##CONST##_##TYPE1##_##TYPE2 (TYPE2 *restrict r, \ + TYPE1 *restrict a, \ + TYPE2 *restrict b) \ + { \ + for (int i = 0; i < COUNT; ++i) \ + r[i] = a[i] > 20 ? b[i] & CONST : 0; \ + } + +#define TEST_ALL(T) \ + T (int32_t, uint16_t, 0xff, 3) \ + \ + T (int64_t, uint16_t, 0xff, 5) \ + T (int64_t, uint32_t, 0xff, 5) \ + T (int64_t, uint32_t, 0xffff, 5) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ + +/* { dg-final { scan-assembler {\tmovprfx\tz[^,]*, p[0-7]/z} } } */ + +/* { dg-final { scan-assembler-not {\tmov\tz[^\n]*z} } } */ +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_8_run.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_8_run.c new file mode 100644 index 00000000000..cfe3ed64818 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_8_run.c @@ -0,0 +1,26 @@ +/* { dg-do run { target { aarch64_sve_hw } } } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_uxt_8.c" + +#define TEST_LOOP(TYPE1, TYPE2, CONST, N) \ + { \ + TYPE1 a[N]; \ + TYPE2 r[N], b[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? -20 - i : 20 + i); \ + b[i] = -5 - i; \ + asm volatile ("" ::: "memory"); \ + } \ + test_##CONST##_##TYPE1##_##TYPE2 (r, a, b); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (TYPE2) (a[i] > 20 ? b[i] & CONST : 0)) \ + __builtin_abort (); \ + } + +int main () +{ + TEST_ALL (TEST_LOOP) + return 0; +}

[pushed] aarch64: Support conditional unpacked UXT on SVE

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