diff mbox series

[committed,AArch64] Fix INSR for zero floats

Message ID mptlfw43hw6.fsf@arm.com
State New
Headers show
Series [committed,AArch64] Fix INSR for zero floats | expand

Commit Message

Richard Sandiford Aug. 7, 2019, 7:16 p.m. UTC 
We used INSR to handle zero integers but not zero floats.

Tested on aarch64-linux-gnu (with and without SVE) and aarch64_be-elf.
Applied as r274193.

Richard


2019-08-07  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/constraints.md (Z): Handle floating-point zeros too.
	* config/aarch64/predicates.md (aarch64_reg_or_zero): Likewise.

gcc/testsuite/
	* gcc.target/aarch64/sve/init_13.c: New test.
diff mbox series

Patch

Index: gcc/config/aarch64/constraints.md
===================================================================
--- gcc/config/aarch64/constraints.md	2019-08-07 19:27:50.000000000 +0100
+++ gcc/config/aarch64/constraints.md	2019-08-07 20:14:16.110034873 +0100
@@ -114,8 +114,8 @@  (define_constraint "Y"
        (match_test "aarch64_float_const_zero_rtx_p (op)")))
 
 (define_constraint "Z"
-  "Integer constant zero."
-  (match_test "op == const0_rtx"))
+  "Integer or floating-point constant zero."
+  (match_test "op == CONST0_RTX (GET_MODE (op))"))
 
 (define_constraint "Ush"
   "A constraint that matches an absolute symbolic address high part."
Index: gcc/config/aarch64/predicates.md
===================================================================
--- gcc/config/aarch64/predicates.md	2019-08-07 19:27:50.000000000 +0100
+++ gcc/config/aarch64/predicates.md	2019-08-07 20:14:16.110034873 +0100
@@ -57,9 +57,9 @@  (define_predicate "aarch64_simd_register
             (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_REGS"))))
 
 (define_predicate "aarch64_reg_or_zero"
-  (and (match_code "reg,subreg,const_int")
+  (and (match_code "reg,subreg,const_int,const_double")
        (ior (match_operand 0 "register_operand")
-	    (match_test "op == const0_rtx"))))
+	    (match_test "op == CONST0_RTX (GET_MODE (op))"))))
 
 (define_predicate "aarch64_reg_or_fp_zero"
   (ior (match_operand 0 "register_operand")
Index: gcc/testsuite/gcc.target/aarch64/sve/init_13.c
===================================================================
--- /dev/null	2019-07-30 08:53:31.317691683 +0100
+++ gcc/testsuite/gcc.target/aarch64/sve/init_13.c	2019-08-07 20:14:16.110034873 +0100
@@ -0,0 +1,17 @@ 
+/* { dg-do assemble { target aarch64_asm_sve_ok } } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+typedef float vnx4sf __attribute__((vector_size (32)));
+
+/*
+** foo:
+**	mov	(z[0-9]+\.s), s0
+**	insr	\1, wzr
+**	...
+*/
+vnx4sf
+foo (float a)
+{
+  return (vnx4sf) { 0.0f, a, a, a, a, a, a, a };
+}