From patchwork Tue Dec 10 16:46:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1207161 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-515621-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="R1sKKp+Y"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47XQvZ564dz9sPc for ; Wed, 11 Dec 2019 03:47:05 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=H0Qhqd7Wkg8IqUYYOCmD7WtBj0NOkknR5rdhz47pnVxNhB4xboQcL duM0ixc7DBd6XCRrKdHSNo+ypqZJhGO6qw0a5wpbk/txra+SIUEgMCP0bVUs4LA0 zuq0uEfHyyc8UUKWcLRfCzCsiQoFfFs9mNYumLDdeSzPNEl2puSHQs= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=lAZqqCpn3cotjYKcP0j8jrRj3wA=; b=R1sKKp+Y8Tj6xjxGjE2O SWI7fOlI7bTBh6xffxNtnb9A6jVz4LJ8XZtJ1AC8LAnNXIoi5XwslgkQFFE0biFq zpLXWfuFf1m2QC0Ej2XPgzIam49kqCAo/2ZmovAs8l7aiG0iw1Y7fAWIkRiZj3xi rVjG4kSY0PV/Cr6fId/HCLY= Received: (qmail 60058 invoked by alias); 10 Dec 2019 16:46:57 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 60048 invoked by uid 89); 10 Dec 2019 16:46:57 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-9.4 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 10 Dec 2019 16:46:56 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2247B1FB for ; Tue, 10 Dec 2019 08:46:55 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.126]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BF2333F6CF for ; Tue, 10 Dec 2019 08:46:54 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [committed][AArch64] Don't allow partial SVE modes in GPRs Date: Tue, 10 Dec 2019 16:46:53 +0000 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 X-IsSubscribed: yes With -msve-vector-bits=N, the payload of some partial SVE modes can be 16 bytes or smaller, which makes them small enough to fit in a pair of GPRs. We specifically don't want that, because the payload is distributed evenly across the SVE register rather than collected at one end. Marshalling it into a GPR via register operations would be expensive. Tested on aarch64-linux-gnu, applied as r279174. Richard 2019-12-10 Richard Sandiford gcc/ * config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Don't allow SVE modes in GPRs. gcc/testsuite/ * gcc.target/aarch64/sve/mixed_size_7.c: New test. Index: gcc/config/aarch64/aarch64.c =================================================================== --- gcc/config/aarch64/aarch64.c 2019-12-05 14:20:17.409060413 +0000 +++ gcc/config/aarch64/aarch64.c 2019-12-10 16:45:42.794317637 +0000 @@ -2019,9 +2019,11 @@ aarch64_hard_regno_mode_ok (unsigned reg if (GP_REGNUM_P (regno)) { + if (vec_flags & VEC_ANY_SVE) + return false; if (known_le (GET_MODE_SIZE (mode), 8)) return true; - else if (known_le (GET_MODE_SIZE (mode), 16)) + if (known_le (GET_MODE_SIZE (mode), 16)) return (regno & 1) == 0; } else if (FP_REGNUM_P (regno)) Index: gcc/testsuite/gcc.target/aarch64/sve/mixed_size_7.c =================================================================== --- /dev/null 2019-09-17 11:41:18.176664108 +0100 +++ gcc/testsuite/gcc.target/aarch64/sve/mixed_size_7.c 2019-12-10 16:45:42.794317637 +0000 @@ -0,0 +1,28 @@ +/* Originally gcc.dg/vect/bb-slp-6.c */ +/* { dg-options "-O2 -ftree-vectorize -msve-vector-bits=256 -fno-vect-cost-model" } */ + +#define N 16 + +unsigned int out[N]; +unsigned int in[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}; + +__attribute__ ((noinline)) int +main1 (unsigned int x, unsigned int y) +{ + int i; + unsigned int *pin = &in[0]; + unsigned int *pout = &out[0]; + unsigned int a0, a1, a2, a3; + + a0 = *pin++ + 23; + a1 = *pin++ + 142; + a2 = *pin++ + 2; + a3 = *pin++ + 31; + + *pout++ = a0 * x; + *pout++ = a1 * y; + *pout++ = a2 * x; + *pout++ = a3 * y; + + return 0; +}