[committed,AArch64] Add support for SVE CNOT

Message ID	mpta7ccnmit.fsf@arm.com
State	New
Headers	show Return-Path: <gcc-patches-return-506891-incoming=patchwork.ozlabs.org@gcc.gnu.org> DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=XJ299CEwzMCqtpKnDbGkEj7KgPDwo5D+PNi6q+T/nJ3VO5jVZvkP0 M3WbVRM1Rf/EAGgQ8dx3ZB9Vr/1eC/3E0u18CkLBabSzPZKI/c5cDYc0R3OJFJmg x6mMoziGn034tQi/73Cu3cViftXKwkp6CM8FOGuH9e+f+YsolXOW+4= Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk Sender: gcc-patches-owner@gcc.gnu.org From: Richard Sandiford <richard.sandiford@arm.com> To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [committed][AArch64] Add support for SVE CNOT Date: Wed, 14 Aug 2019 10:07:06 +0100 Message-ID: <mpta7ccnmit.fsf@arm.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain
Series	[committed,AArch64] Add support for SVE CNOT \| expand [committed,AArch64] Add support for SVE CNOT

Index: gcc/config/aarch64/predicates.md =================================================================== --- gcc/config/aarch64/predicates.md 2019-08-14 09:58:35.914942337 +0100 +++ gcc/config/aarch64/predicates.md 2019-08-14 10:04:58.948129300 +0100 @@ -460,6 +460,10 @@ (define_predicate "aarch64_simd_imm_zero (and (match_code "const,const_vector") (match_test "op == CONST0_RTX (GET_MODE (op))"))) +(define_predicate "aarch64_simd_imm_one" + (and (match_code "const_vector") + (match_test "op == CONST1_RTX (GET_MODE (op))"))) + (define_predicate "aarch64_simd_or_scalar_imm_zero" (and (match_code "const_int,const_double,const,const_vector") (match_test "op == CONST0_RTX (GET_MODE (op))"))) Index: gcc/config/aarch64/aarch64-sve.md =================================================================== --- gcc/config/aarch64/aarch64-sve.md 2019-08-14 10:02:44.165119259 +0100 +++ gcc/config/aarch64/aarch64-sve.md 2019-08-14 10:04:58.948129300 +0100 @@ -54,6 +54,7 @@ ;; ;; == Unary arithmetic ;; ---- [INT] General unary arithmetic corresponding to rtx codes +;; ---- [INT] Logical inverse ;; ---- [FP] General unary arithmetic corresponding to unspecs ;; ---- [PRED] Inverse @@ -1455,6 +1456,95 @@ (define_insn "*<optab><mode>2" ) ;; ------------------------------------------------------------------------- +;; ---- [INT] Logical inverse +;; ------------------------------------------------------------------------- + +;; Predicated logical inverse. +(define_insn "*cnot<mode>" + [(set (match_operand:SVE_I 0 "register_operand" "=w") + (unspec:SVE_I + [(unspec:<VPRED> + [(match_operand:<VPRED> 1 "register_operand" "Upl") + (match_operand:SI 5 "aarch64_sve_ptrue_flag") + (eq:<VPRED> + (match_operand:SVE_I 2 "register_operand" "w") + (match_operand:SVE_I 3 "aarch64_simd_imm_zero"))] + UNSPEC_PRED_Z) + (match_operand:SVE_I 4 "aarch64_simd_imm_one") + (match_dup 3)] + UNSPEC_SEL))] + "TARGET_SVE" + "cnot\t%0.<Vetype>, %1/m, %2.<Vetype>" +) + +;; Predicated logical inverse, merging with the first input. +(define_insn_and_rewrite "*cond_cnot<mode>_2" + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") + (unspec:SVE_I + [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl") + ;; Logical inverse of operand 2 (as above). + (unspec:SVE_I + [(unspec:<VPRED> + [(match_operand 5) + (const_int SVE_KNOWN_PTRUE) + (eq:<VPRED> + (match_operand:SVE_I 2 "register_operand" "0, w") + (match_operand:SVE_I 3 "aarch64_simd_imm_zero"))] + UNSPEC_PRED_Z) + (match_operand:SVE_I 4 "aarch64_simd_imm_one") + (match_dup 3)] + UNSPEC_SEL) + (match_dup 2)] + UNSPEC_SEL))] + "TARGET_SVE" + "@ + cnot\t%0.<Vetype>, %1/m, %0.<Vetype> + movprfx\t%0, %2\;cnot\t%0.<Vetype>, %1/m, %2.<Vetype>" + "&& !CONSTANT_P (operands[5])" + { + operands[5] = CONSTM1_RTX (<VPRED>mode); + } + [(set_attr "movprfx" "*,yes")] +) + +;; Predicated logical inverse, merging with an independent value. +;; +;; The earlyclobber isn't needed for the first alternative, but omitting +;; it would only help the case in which operands 2 and 6 are the same, +;; which is handled above rather than here. Marking all the alternatives +;; as earlyclobber helps to make the instruction more regular to the +;; register allocator. +(define_insn_and_rewrite "*cond_cnot<mode>_any" + [(set (match_operand:SVE_I 0 "register_operand" "=&w, ?&w, ?&w") + (unspec:SVE_I + [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl") + ;; Logical inverse of operand 2 (as above). + (unspec:SVE_I + [(unspec:<VPRED> + [(match_operand 5) + (const_int SVE_KNOWN_PTRUE) + (eq:<VPRED> + (match_operand:SVE_I 2 "register_operand" "w, w, w") + (match_operand:SVE_I 3 "aarch64_simd_imm_zero"))] + UNSPEC_PRED_Z) + (match_operand:SVE_I 4 "aarch64_simd_imm_one") + (match_dup 3)] + UNSPEC_SEL) + (match_operand:SVE_I 6 "aarch64_simd_reg_or_zero" "0, Dz, w")] + UNSPEC_SEL))] + "TARGET_SVE && !rtx_equal_p (operands[2], operands[6])" + "@ + cnot\t%0.<Vetype>, %1/m, %2.<Vetype> + movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;cnot\t%0.<Vetype>, %1/m, %2.<Vetype> + movprfx\t%0, %6\;cnot\t%0.<Vetype>, %1/m, %2.<Vetype>" + "&& !CONSTANT_P (operands[5])" + { + operands[5] = CONSTM1_RTX (<VPRED>mode); + } + [(set_attr "movprfx" "*,yes,yes")] +) + +;; ------------------------------------------------------------------------- ;; ---- [FP] General unary arithmetic corresponding to unspecs ;; ------------------------------------------------------------------------- ;; Includes: Index: gcc/testsuite/gcc.target/aarch64/sve/cnot_1.c =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/gcc.target/aarch64/sve/cnot_1.c 2019-08-14 10:04:58.948129300 +0100 @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include <stdint.h> + +#define DEF_LOOP(TYPE) \ + void __attribute__ ((noipa)) \ + test_##TYPE (TYPE *restrict r, TYPE *restrict a, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = !a[i]; \ + } + +#define TEST_ALL(T) \ + T (int8_t) \ + T (int16_t) \ + T (int32_t) \ + T (int64_t) \ + T (uint8_t) \ + T (uint16_t) \ + T (uint32_t) \ + T (uint64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ +/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d\n} 2 } } */ Index: gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_1.c =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_1.c 2019-08-14 10:04:58.948129300 +0100 @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include <stdint.h> + +#define DEF_LOOP(TYPE) \ + void __attribute__ ((noipa)) \ + test_##TYPE (TYPE *__restrict r, TYPE *__restrict a, \ + TYPE *__restrict b, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = a[i] == 0 ? !b[i] : b[i]; \ + } + +#define TEST_ALL(T) \ + T (int8_t) \ + T (uint8_t) \ + T (int16_t) \ + T (uint16_t) \ + T (int32_t) \ + T (uint32_t) \ + T (int64_t) \ + T (uint64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.b, p[0-7]/m,} 2 } } */ +/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.h, p[0-7]/m,} 2 } } */ +/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.s, p[0-7]/m,} 2 } } */ +/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.d, p[0-7]/m,} 2 } } */ + +/* { dg-final { scan-assembler-not {\tmov\tz} } } */ +/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */ +/* Currently we canonicalize the ?: so that !b[i] is the "false" value. */ +/* { dg-final { scan-assembler-not {\tsel\t} { xfail *-*-* } } } */ Index: gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_1_run.c =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_1_run.c 2019-08-14 10:04:58.948129300 +0100 @@ -0,0 +1,32 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_cnot_1.c" + +#define N 99 + +#define TEST_LOOP(TYPE) \ + { \ + TYPE r[N], a[N], b[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i % 3) < (i % 5); \ + b[i] = i % 7 < 3; \ + asm volatile ("" ::: "memory"); \ + } \ + test_##TYPE (r, a, b, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = a[i] == 0 ? !b[i] : b[i]; \ + if (r[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_LOOP) + return 0; +} Index: gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_2.c =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_2.c 2019-08-14 10:04:58.948129300 +0100 @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include <stdint.h> + +#define DEF_LOOP(TYPE) \ + void __attribute__ ((noipa)) \ + test_##TYPE (TYPE *__restrict r, TYPE *__restrict a, \ + TYPE *__restrict b, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = a[i] == 0 ? !b[i] : a[i]; \ + } + +#define TEST_ALL(T) \ + T (int8_t) \ + T (uint8_t) \ + T (int16_t) \ + T (uint16_t) \ + T (int32_t) \ + T (uint32_t) \ + T (int64_t) \ + T (uint64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.b, p[0-7]/m,} 2 } } */ +/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.h, p[0-7]/m,} 2 } } */ +/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.s, p[0-7]/m,} 2 } } */ +/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.d, p[0-7]/m,} 2 } } */ + +/* { dg-final { scan-assembler-not {\tmov\tz} } } */ +/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */ +/* Currently we canonicalize the ?: so that !b[i] is the "false" value. */ +/* { dg-final { scan-assembler-not {\tsel\t} { xfail *-*-* } } } */ Index: gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_2_run.c =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_2_run.c 2019-08-14 10:04:58.948129300 +0100 @@ -0,0 +1,32 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_cnot_2.c" + +#define N 99 + +#define TEST_LOOP(TYPE) \ + { \ + TYPE r[N], a[N], b[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i % 3) < (i % 5); \ + b[i] = i % 7 < 3; \ + asm volatile ("" ::: "memory"); \ + } \ + test_##TYPE (r, a, b, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = a[i] == 0 ? !b[i] : a[i]; \ + if (r[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_LOOP) + return 0; +} Index: gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_3.c =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_3.c 2019-08-14 10:04:58.948129300 +0100 @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include <stdint.h> + +#define DEF_LOOP(TYPE) \ + void __attribute__ ((noipa)) \ + test_##TYPE (TYPE *__restrict r, TYPE *__restrict a, \ + TYPE *__restrict b, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = a[i] == 0 ? !b[i] : 127; \ + } + +#define TEST_ALL(T) \ + T (int8_t) \ + T (uint8_t) \ + T (int16_t) \ + T (uint16_t) \ + T (int32_t) \ + T (uint32_t) \ + T (int64_t) \ + T (uint64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.b, p[0-7]/m,} 2 } } */ +/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.h, p[0-7]/m,} 2 } } */ +/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.s, p[0-7]/m,} 2 } } */ +/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.d, p[0-7]/m,} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+, z[0-9]+\n} 8 } } */ + +/* { dg-final { scan-assembler-not {\tmov\tz[^\n]*z} } } */ +/* { dg-final { scan-assembler-not {\tsel\t} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_3_run.c =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_3_run.c 2019-08-14 10:04:58.948129300 +0100 @@ -0,0 +1,32 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_cnot_3.c" + +#define N 99 + +#define TEST_LOOP(TYPE) \ + { \ + TYPE r[N], a[N], b[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i % 3) < (i % 5); \ + b[i] = i % 7 < 3; \ + asm volatile ("" ::: "memory"); \ + } \ + test_##TYPE (r, a, b, N); \ + for (int i = 0; i < N; ++i) \ + { \ + TYPE expected = a[i] == 0 ? !b[i] : 127; \ + if (r[i] != expected) \ + __builtin_abort (); \ + asm volatile ("" ::: "memory"); \ + } \ + } + +int +main (void) +{ + TEST_ALL (TEST_LOOP) + return 0; +}

[committed,AArch64] Add support for SVE CNOT

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