From patchwork Tue Jun 18 14:49:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1117993 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-503181-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="aQmtcWlj"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45SrbH34txz9sBr for ; Wed, 19 Jun 2019 00:50:03 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=u+8z/H/a5XeEOoScKBfCH8bzseLW5AQJDfI4IV2RYQOfHaotgxrhg InMochfnfqItwcmx4rhSyGY+M0y5pOp236IPFJnKInAx4Cfz81peqMD7V5catziu 4kXWaHSWt1zAmD++2gHXyxdjL/byt5c8Qq8KaRLrpn3owWrIKKYzns= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=5bXhy5i3R3uq2ypuHc5HVjG1Ceo=; b=aQmtcWlj4ISSbjoMkAwM RlsHErFIs3+2pF/VfmuiS8wXACAKcQgKX6xtccjm96pac39KFdMNQiSeiIIfYiAh c6hhr2TS+GwoR6IMoBQUNApSwQtxPFXFZFEiHjAYe52whYkZrh3QtQuu3EjC6/Gq RnMJqnHCMVhkoZ/KAMyUtv4= Received: (qmail 87861 invoked by alias); 18 Jun 2019 14:49:55 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 87782 invoked by uid 89); 18 Jun 2019 14:49:54 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-7.5 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS autolearn=ham version=3.3.1 spammy=abd, throughout, 23227 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 18 Jun 2019 14:49:51 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 59C0C2B for ; Tue, 18 Jun 2019 07:49:50 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.39]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D8DD13F718 for ; Tue, 18 Jun 2019 07:49:49 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [committed][AArch64] Factor out ptrue predicate creation Date: Tue, 18 Jun 2019 15:49:48 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 This is the first step to canonicalising predicate constants so that they can be reused between modes. Tested on aarch64-linux-gnu (with and without SVE). Applied as Richard 2019-06-18 Richard Sandiford gcc/ * config/aarch64/aarch64-protos.h (aarch64_ptrue_reg): Declare. * config/aarch64/aarch64.c (aarch64_ptrue_reg): New functions. (aarch64_expand_sve_widened_duplicate, aarch64_expand_sve_mem_move) (aarch64_maybe_expand_sve_subreg_move, aarch64_evpc_rev_local) (aarch64_expand_sve_vec_cmp_int): Use it. (aarch64_expand_sve_vec_cmp_float): Likewise. * config/aarch64/aarch64-sve.md: Likewise throughout. Index: gcc/config/aarch64/aarch64-protos.h =================================================================== --- gcc/config/aarch64/aarch64-protos.h 2019-06-07 08:39:40.998350935 +0100 +++ gcc/config/aarch64/aarch64-protos.h 2019-06-18 15:42:18.535817057 +0100 @@ -520,6 +520,7 @@ const char * aarch64_output_probe_sve_st void aarch64_err_no_fpadvsimd (machine_mode); void aarch64_expand_epilogue (bool); void aarch64_expand_mov_immediate (rtx, rtx, rtx (*) (rtx, rtx) = 0); +rtx aarch64_ptrue_reg (machine_mode); void aarch64_emit_sve_pred_move (rtx, rtx, rtx); void aarch64_expand_sve_mem_move (rtx, rtx, machine_mode); bool aarch64_maybe_expand_sve_subreg_move (rtx, rtx); Index: gcc/config/aarch64/aarch64.c =================================================================== --- gcc/config/aarch64/aarch64.c 2019-06-18 09:35:55.205867120 +0100 +++ gcc/config/aarch64/aarch64.c 2019-06-18 15:42:18.539817024 +0100 @@ -2458,6 +2458,15 @@ aarch64_force_temporary (machine_mode mo } } +/* Return an all-true predicate register of mode MODE. */ + +rtx +aarch64_ptrue_reg (machine_mode mode) +{ + gcc_assert (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL); + return force_reg (mode, CONSTM1_RTX (mode)); +} + /* Return true if we can move VALUE into a register using a single CNT[BHWD] instruction. */ @@ -3187,7 +3196,7 @@ aarch64_expand_sve_widened_duplicate (rt machine_mode mode = GET_MODE (dest); unsigned int elem_bytes = GET_MODE_UNIT_SIZE (mode); machine_mode pred_mode = aarch64_sve_pred_mode (elem_bytes).require (); - rtx ptrue = force_reg (pred_mode, CONSTM1_RTX (pred_mode)); + rtx ptrue = aarch64_ptrue_reg (pred_mode); src = gen_rtx_UNSPEC (mode, gen_rtvec (2, ptrue, src), UNSPEC_LD1RQ); emit_insn (gen_rtx_SET (dest, src)); return true; @@ -3448,7 +3457,7 @@ aarch64_emit_sve_pred_move (rtx dest, rt aarch64_expand_sve_mem_move (rtx dest, rtx src, machine_mode pred_mode) { machine_mode mode = GET_MODE (dest); - rtx ptrue = force_reg (pred_mode, CONSTM1_RTX (pred_mode)); + rtx ptrue = aarch64_ptrue_reg (pred_mode); if (!register_operand (src, mode) && !register_operand (dest, mode)) { @@ -3512,7 +3521,7 @@ aarch64_maybe_expand_sve_subreg_move (rt return false; /* Generate *aarch64_sve_mov_subreg_be. */ - rtx ptrue = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode)); + rtx ptrue = aarch64_ptrue_reg (VNx16BImode); rtx unspec = gen_rtx_UNSPEC (GET_MODE (dest), gen_rtvec (2, ptrue, src), UNSPEC_REV_SUBREG); emit_insn (gen_rtx_SET (dest, unspec)); @@ -16753,7 +16762,7 @@ aarch64_evpc_rev_local (struct expand_ve rtx src = gen_rtx_UNSPEC (d->vmode, gen_rtvec (1, d->op0), unspec); if (d->vec_flags == VEC_SVE_DATA) { - rtx pred = force_reg (pred_mode, CONSTM1_RTX (pred_mode)); + rtx pred = aarch64_ptrue_reg (pred_mode); src = gen_rtx_UNSPEC (d->vmode, gen_rtvec (2, pred, src), UNSPEC_MERGE_PTRUE); } @@ -17101,7 +17110,7 @@ aarch64_expand_sve_vec_cmp_int (rtx targ if (!aarch64_sve_cmp_operand_p (code, op1)) op1 = force_reg (data_mode, op1); - rtx ptrue = force_reg (pred_mode, CONSTM1_RTX (pred_mode)); + rtx ptrue = aarch64_ptrue_reg (pred_mode); rtx cond = gen_rtx_fmt_ee (code, pred_mode, op0, op1); aarch64_emit_sve_ptrue_op_cc (target, ptrue, cond); } @@ -17160,7 +17169,7 @@ aarch64_expand_sve_vec_cmp_float (rtx ta machine_mode pred_mode = GET_MODE (target); machine_mode data_mode = GET_MODE (op0); - rtx ptrue = force_reg (pred_mode, CONSTM1_RTX (pred_mode)); + rtx ptrue = aarch64_ptrue_reg (pred_mode); switch (code) { case UNORDERED: Index: gcc/config/aarch64/aarch64-sve.md =================================================================== --- gcc/config/aarch64/aarch64-sve.md 2019-06-18 15:41:32.604198094 +0100 +++ gcc/config/aarch64/aarch64-sve.md 2019-06-18 15:42:18.535817057 +0100 @@ -232,7 +232,7 @@ (define_expand "gather_load" UNSPEC_LD1_GATHER))] "TARGET_SVE" { - operands[5] = force_reg (mode, CONSTM1_RTX (mode)); + operands[5] = aarch64_ptrue_reg (mode); } ) @@ -289,7 +289,7 @@ (define_expand "scatter_store" UNSPEC_ST1_SCATTER))] "TARGET_SVE" { - operands[5] = force_reg (mode, CONSTM1_RTX (mode)); + operands[5] = aarch64_ptrue_reg (mode); } ) @@ -629,7 +629,7 @@ (define_expand "vec_duplicate" { if (MEM_P (operands[1])) { - rtx ptrue = force_reg (mode, CONSTM1_RTX (mode)); + rtx ptrue = aarch64_ptrue_reg (mode); emit_insn (gen_sve_ld1r (operands[0], ptrue, operands[1], CONST0_RTX (mode))); DONE; @@ -744,7 +744,7 @@ (define_expand "vec_load_lanesmode, CONSTM1_RTX (mode)); + operands[2] = aarch64_ptrue_reg (mode); } ) @@ -773,7 +773,7 @@ (define_expand "vec_store_lanesmode, CONSTM1_RTX (mode)); + operands[2] = aarch64_ptrue_reg (mode); } ) @@ -932,7 +932,7 @@ (define_expand "mul3" UNSPEC_MERGE_PTRUE))] "TARGET_SVE" { - operands[3] = force_reg (mode, CONSTM1_RTX (mode)); + operands[3] = aarch64_ptrue_reg (mode); } ) @@ -1019,7 +1019,7 @@ (define_expand "mul3_highpart" UNSPEC_MERGE_PTRUE))] "TARGET_SVE" { - operands[3] = force_reg (mode, CONSTM1_RTX (mode)); + operands[3] = aarch64_ptrue_reg (mode); } ) @@ -1050,7 +1050,7 @@ (define_expand "3" UNSPEC_MERGE_PTRUE))] "TARGET_SVE" { - operands[3] = force_reg (mode, CONSTM1_RTX (mode)); + operands[3] = aarch64_ptrue_reg (mode); } ) @@ -1080,7 +1080,7 @@ (define_expand "2" UNSPEC_MERGE_PTRUE))] "TARGET_SVE" { - operands[2] = force_reg (mode, CONSTM1_RTX (mode)); + operands[2] = aarch64_ptrue_reg (mode); } ) @@ -1150,7 +1150,7 @@ (define_expand "3" (match_dup 3)))] "TARGET_SVE" { - operands[3] = force_reg (mode, CONSTM1_RTX (mode)); + operands[3] = aarch64_ptrue_reg (mode); } ) @@ -1197,7 +1197,7 @@ (define_expand "one_cmpl2" (match_dup 2)))] "TARGET_SVE" { - operands[2] = force_reg (mode, CONSTM1_RTX (mode)); + operands[2] = aarch64_ptrue_reg (mode); } ) @@ -1246,7 +1246,7 @@ (define_expand "v3" UNSPEC_MERGE_PTRUE))] "TARGET_SVE" { - operands[3] = force_reg (mode, CONSTM1_RTX (mode)); + operands[3] = aarch64_ptrue_reg (mode); } ) @@ -1738,7 +1738,7 @@ (define_expand "cbranch4" (pc)))] "" { - rtx ptrue = force_reg (mode, CONSTM1_RTX (mode)); + rtx ptrue = aarch64_ptrue_reg (mode); rtx pred; if (operands[2] == CONST0_RTX (mode)) pred = operands[1]; @@ -1764,7 +1764,7 @@ (define_expand "3" UNSPEC_MERGE_PTRUE))] "TARGET_SVE" { - operands[3] = force_reg (mode, CONSTM1_RTX (mode)); + operands[3] = aarch64_ptrue_reg (mode); } ) @@ -1793,7 +1793,7 @@ (define_expand "3" UNSPEC_MERGE_PTRUE))] "TARGET_SVE" { - operands[3] = force_reg (mode, CONSTM1_RTX (mode)); + operands[3] = aarch64_ptrue_reg (mode); } ) @@ -1823,7 +1823,7 @@ (define_expand "3" UNSPEC_MERGE_PTRUE))] "TARGET_SVE" { - operands[3] = force_reg (mode, CONSTM1_RTX (mode)); + operands[3] = aarch64_ptrue_reg (mode); } ) @@ -2017,7 +2017,7 @@ (define_expand "reduc_plus_scal_" UNSPEC_ADDV))] "TARGET_SVE" { - operands[2] = force_reg (mode, CONSTM1_RTX (mode)); + operands[2] = aarch64_ptrue_reg (mode); } ) @@ -2039,7 +2039,7 @@ (define_expand "reduc_plus_scal_" UNSPEC_FADDV))] "TARGET_SVE" { - operands[2] = force_reg (mode, CONSTM1_RTX (mode)); + operands[2] = aarch64_ptrue_reg (mode); } ) @@ -2061,7 +2061,7 @@ (define_expand "reduc__scal_ MAXMINV))] "TARGET_SVE" { - operands[2] = force_reg (mode, CONSTM1_RTX (mode)); + operands[2] = aarch64_ptrue_reg (mode); } ) @@ -2083,7 +2083,7 @@ (define_expand "reduc__scal_ FMAXMINV))] "TARGET_SVE" { - operands[2] = force_reg (mode, CONSTM1_RTX (mode)); + operands[2] = aarch64_ptrue_reg (mode); } ) @@ -2104,7 +2104,7 @@ (define_expand "reduc__scal_mode, CONSTM1_RTX (mode)); + operands[2] = aarch64_ptrue_reg (mode); } ) @@ -2126,7 +2126,7 @@ (define_expand "fold_left_plus_" UNSPEC_FADDA))] "TARGET_SVE" { - operands[3] = force_reg (mode, CONSTM1_RTX (mode)); + operands[3] = aarch64_ptrue_reg (mode); } ) @@ -2167,7 +2167,7 @@ (define_expand "add3" UNSPEC_MERGE_PTRUE))] "TARGET_SVE" { - operands[3] = force_reg (mode, CONSTM1_RTX (mode)); + operands[3] = aarch64_ptrue_reg (mode); } ) @@ -2203,7 +2203,7 @@ (define_expand "sub3" UNSPEC_MERGE_PTRUE))] "TARGET_SVE" { - operands[3] = force_reg (mode, CONSTM1_RTX (mode)); + operands[3] = aarch64_ptrue_reg (mode); } ) @@ -2243,7 +2243,7 @@ (define_expand "mul3" UNSPEC_MERGE_PTRUE))] "TARGET_SVE" { - operands[3] = force_reg (mode, CONSTM1_RTX (mode)); + operands[3] = aarch64_ptrue_reg (mode); } ) @@ -2289,7 +2289,7 @@ (define_expand "fma4" UNSPEC_MERGE_PTRUE))] "TARGET_SVE" { - operands[4] = force_reg (mode, CONSTM1_RTX (mode)); + operands[4] = aarch64_ptrue_reg (mode); } ) @@ -2322,7 +2322,7 @@ (define_expand "fnma4" UNSPEC_MERGE_PTRUE))] "TARGET_SVE" { - operands[4] = force_reg (mode, CONSTM1_RTX (mode)); + operands[4] = aarch64_ptrue_reg (mode); } ) @@ -2356,7 +2356,7 @@ (define_expand "fms4" UNSPEC_MERGE_PTRUE))] "TARGET_SVE" { - operands[4] = force_reg (mode, CONSTM1_RTX (mode)); + operands[4] = aarch64_ptrue_reg (mode); } ) @@ -2391,7 +2391,7 @@ (define_expand "fnms4" UNSPEC_MERGE_PTRUE))] "TARGET_SVE" { - operands[4] = force_reg (mode, CONSTM1_RTX (mode)); + operands[4] = aarch64_ptrue_reg (mode); } ) @@ -2424,7 +2424,7 @@ (define_expand "div3" UNSPEC_MERGE_PTRUE))] "TARGET_SVE" { - operands[3] = force_reg (mode, CONSTM1_RTX (mode)); + operands[3] = aarch64_ptrue_reg (mode); } ) @@ -2453,7 +2453,7 @@ (define_expand "2" UNSPEC_MERGE_PTRUE))] "TARGET_SVE" { - operands[2] = force_reg (mode, CONSTM1_RTX (mode)); + operands[2] = aarch64_ptrue_reg (mode); } ) @@ -2491,7 +2491,7 @@ (define_expand "2" UNSPEC_MERGE_PTRUE))] "TARGET_SVE" { - operands[2] = force_reg (mode, CONSTM1_RTX (mode)); + operands[2] = aarch64_ptrue_reg (mode); } ) @@ -2518,7 +2518,7 @@ (define_expand "< UNSPEC_MERGE_PTRUE))] "TARGET_SVE" { - operands[2] = force_reg (mode, CONSTM1_RTX (mode)); + operands[2] = aarch64_ptrue_reg (mode); } ) @@ -2569,7 +2569,7 @@ (define_expand "mode, CONSTM1_RTX (mode)); + operands[2] = aarch64_ptrue_reg (mode); } ) @@ -2707,7 +2707,7 @@ (define_expand "vec_unpacks__ ? gen_aarch64_sve_zip2 : gen_aarch64_sve_zip1) (temp, operands[1], operands[1])); - rtx ptrue = force_reg (mode, CONSTM1_RTX (mode)); + rtx ptrue = aarch64_ptrue_reg (mode); emit_insn (gen_aarch64_sve_extend2 (operands[0], ptrue, temp)); DONE; @@ -2733,7 +2733,7 @@ (define_expand "vec_unpack_flo ? gen_aarch64_sve_zip2vnx4si : gen_aarch64_sve_zip1vnx4si) (temp, operands[1], operands[1])); - rtx ptrue = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode)); + rtx ptrue = aarch64_ptrue_reg (VNx2BImode); emit_insn (gen_aarch64_sve_vnx4sivnx2df2 (operands[0], ptrue, temp)); DONE; @@ -2783,7 +2783,7 @@ (define_expand "vec_pack_trunc_" (unspec:SVE_HSF [(match_dup 4) (match_dup 5)] UNSPEC_UZP1))] "TARGET_SVE" { - operands[3] = force_reg (mode, CONSTM1_RTX (mode)); + operands[3] = aarch64_ptrue_reg (mode); operands[4] = gen_reg_rtx (mode); operands[5] = gen_reg_rtx (mode); } @@ -2805,7 +2805,7 @@ (define_expand "vec_pack_fix_trunc_v (unspec:VNx4SI [(match_dup 4) (match_dup 5)] UNSPEC_UZP1))] "TARGET_SVE" { - operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode)); + operands[3] = aarch64_ptrue_reg (VNx2BImode); operands[4] = gen_reg_rtx (VNx4SImode); operands[5] = gen_reg_rtx (VNx4SImode); } @@ -3073,7 +3073,7 @@ (define_expand "abd_3" (match_operand:SVE_I 2 "register_operand"))] "TARGET_SVE" { - rtx pred = force_reg (mode, CONSTM1_RTX (mode)); + rtx pred = aarch64_ptrue_reg (mode); emit_insn (gen_aarch64_abd_3 (operands[0], pred, operands[1], operands[2])); DONE;