From patchwork Wed Jul 20 13:47:12 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 105693 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 85959B6F6F for ; Wed, 20 Jul 2011 23:47:37 +1000 (EST) Received: (qmail 15784 invoked by alias); 20 Jul 2011 13:47:36 -0000 Received: (qmail 15776 invoked by uid 22791); 20 Jul 2011 13:47:35 -0000 X-SWARE-Spam-Status: No, hits=-2.4 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, TW_EG, TW_GC X-Spam-Check-By: sourceware.org Received: from mail-fx0-f49.google.com (HELO mail-fx0-f49.google.com) (209.85.161.49) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 20 Jul 2011 13:47:16 +0000 Received: by fxd20 with SMTP id 20so1389131fxd.22 for ; Wed, 20 Jul 2011 06:47:15 -0700 (PDT) Received: by 10.223.1.129 with SMTP id 1mr248086faf.103.1311169635407; Wed, 20 Jul 2011 06:47:15 -0700 (PDT) Received: from richards-thinkpad (gbibp9ph1--blueice3n2.emea.ibm.com [195.212.29.84]) by mx.google.com with ESMTPS id 22sm693502fas.11.2011.07.20.06.47.13 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 20 Jul 2011 06:47:14 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@linaro.org Subject: Make regcprop check HARD_REGNO_MODE_OK Date: Wed, 20 Jul 2011 14:47:12 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.1 (gnu/linux) MIME-Version: 1.0 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org This patch makes regcprop check HARD_REGNO_MODE_OK before creating a hard register in a different mode. It fixes a segfault in a build of bionic on ARM. The missing check usually doesn't cause problems. The define_insn constraints are likely to reject invalid registers for "real" insns, while debug insns are often able to get away with them without triggering an ICE. It only showed up on ARM because a debug insn used (reg:SI d16), and arm_dwarf_register_span returned a zero-length parallel for this (invalid) case. The host compiler also happened not to optimise away the dead size assignment described here: http://gcc.gnu.org/ml/gcc/2011-07/msg00376.html so we would seg trying to access beyond the end of the vector. Tested on x86_64-linux-gnu and arm-linux-gnueabi. OK to install? Richard gcc/ * regcprop.c (maybe_mode_change): Check HARD_REGNO_MODE_OK. Index: gcc/regcprop.c =================================================================== --- gcc/regcprop.c 2011-06-22 16:46:35.000000000 +0100 +++ gcc/regcprop.c 2011-07-20 13:04:37.000000000 +0100 @@ -418,10 +418,9 @@ maybe_mode_change (enum machine_mode ori offset = ((WORDS_BIG_ENDIAN ? wordoffset : 0) + (BYTES_BIG_ENDIAN ? byteoffset : 0)); - return gen_rtx_raw_REG (new_mode, - regno + subreg_regno_offset (regno, orig_mode, - offset, - new_mode)); + regno += subreg_regno_offset (regno, orig_mode, offset, new_mode); + if (HARD_REGNO_MODE_OK (regno, new_mode)) + return gen_rtx_raw_REG (new_mode, regno); } return NULL_RTX; }