diff mbox series

[1/4] rs6000: Change the length attribute default

Message ID fb6dba35e85055af00c83fd53c17d61efdd82e71.1534361927.git.segher@kernel.crashing.org
State New
Headers show
Series rs6000: length attribute | expand

Commit Message

Segher Boessenkool Aug. 16, 2018, 5:14 p.m. UTC 
This moves what is currently the default of the length attribute to
the only branch instruction patterns where it applies, namely, the
B-form instructions.  It was used for the "jump" instruction as well
before, but that is an I-form instruction and always has length 4.


2018-08-16  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/rs6000.md (length): Always define as const_int 4.
	(unnamed conditional branch define_insn): Set length to 4 or 8
	depending on offset.
	(<bd>_<mode>): Similar, for alternative 0.
	(<bd>tf_<mode>): Ditto.

---
 gcc/config/rs6000/rs6000.md | 47 ++++++++++++++++++++++++++++++---------------
 1 file changed, 32 insertions(+), 15 deletions(-)
diff mbox series

Patch

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index d70b01b..45e42ff 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -243,18 +243,8 @@  (define_attr "var_shift" "no,yes"
 ;; Is copying of this instruction disallowed?
 (define_attr "cannot_copy" "no,yes" (const_string "no"))
 
-;; Length (in bytes).
-; '(pc)' in the following doesn't include the instruction itself; it is
-; calculated as if the instruction had zero size.
-(define_attr "length" ""
-  (if_then_else (eq_attr "type" "branch")
-		(if_then_else (and (ge (minus (match_dup 0) (pc))
-				       (const_int -32768))
-				   (lt (minus (match_dup 0) (pc))
-				       (const_int 32764)))
-			      (const_int 4)
-			      (const_int 8))
-		(const_int 4)))
+;; Length of the instruction (in bytes).
+(define_attr "length" "" (const_int 4))
 
 ;; Processor type -- this attribute must exactly match the processor_type
 ;; enumeration in rs6000-opts.h.
@@ -12346,7 +12336,14 @@  (define_insn ""
 {
   return output_cbranch (operands[1], "%l0", 0, insn);
 }
-  [(set_attr "type" "branch")])
+  [(set_attr "type" "branch")
+   (set (attr "length")
+	(if_then_else (and (ge (minus (match_dup 0) (pc))
+			       (const_int -32768))
+			   (lt (minus (match_dup 0) (pc))
+			       (const_int 32764)))
+		      (const_int 4)
+		      (const_int 8)))])
 
 (define_insn ""
   [(set (pc)
@@ -12716,7 +12713,17 @@  (define_insn "<bd>_<mode>"
     return "<bd_neg> $+8\;b %l0";
 }
   [(set_attr "type" "branch")
-   (set_attr "length" "*,16,20,20")])
+   (set (attr "length")
+	(cond [(eq (symbol_ref "which_alternative") (const_int 0))
+		  (if_then_else (and (ge (minus (match_dup 0) (pc))
+					 (const_int -32768))
+				     (lt (minus (match_dup 0) (pc))
+					 (const_int 32764)))
+				(const_int 4)
+				(const_int 8))
+	       (eq (symbol_ref "which_alternative") (const_int 1))
+		  (const_int 16)]
+	   (const_int 20)))])
 
 ;; Now the splitter if we could not allocate the CTR register
 (define_split
@@ -12795,7 +12802,17 @@  (define_insn "<bd>tf_<mode>"
     }
 }
   [(set_attr "type" "branch")
-   (set_attr "length" "*,16,20,20")])
+   (set (attr "length")
+	(cond [(eq (symbol_ref "which_alternative") (const_int 0))
+		  (if_then_else (and (ge (minus (match_dup 0) (pc))
+					 (const_int -32768))
+				     (lt (minus (match_dup 0) (pc))
+					 (const_int 32764)))
+				(const_int 4)
+				(const_int 8))
+	       (eq (symbol_ref "which_alternative") (const_int 1))
+		  (const_int 16)]
+	     (const_int 20)))])
 
 ;; Now the splitter if we could not allocate the CTR register
 (define_split