| Message ID | fa1492cd-15f2-eeb1-020a-5122ba51b59b@codesourcery.com |
|---|---|
| State | New |
| Headers | show |
| Series | [AMDGCN] Skip test gcc/testsuite/gcc.dg/asm-4.c | expand |
On 05/12/2019 07:05, Harwath, Frederik wrote: > Hi, > the inline assembly "p" modifier ("An operand that is a valid memory address is allowed", > cf. https://gcc.gnu.org/onlinedocs/gcc/Simple-Constraints.html#Simple-Constraints) > is not supported on AMD GCN. This causes an ICE during the compilation of gcc.dg/asm-4.c. > We should skip the test for the amdgcn-*-* target. For the record (should anyone else reading this wonder), it is not supported because the many address spaces and their differing register constraints make the question of what is "a valid memory address" somewhat nebulous. GCN assembler should use 'RF' or 'RM', for most purposes ('RB', 'RS', 'RL', 'RG', and 'RD' are also available). > Can I merge the patch below into trunk? Yes. Andrew
Index: gcc/testsuite/gcc.dg/asm-4.c =================================================================== --- gcc/testsuite/gcc.dg/asm-4.c (revision 278932) +++ gcc/testsuite/gcc.dg/asm-4.c (working copy) @@ -3,6 +3,7 @@ /* "p" modifier can't be used to generate a valid memory address with ILP32. */ /* { dg-skip-if "" { aarch64*-*-* && ilp32 } } */ +/* { dg-skip-if "'p' is not supported for GCN" { amdgcn-*-* } } */ int main() {
Hi, the inline assembly "p" modifier ("An operand that is a valid memory address is allowed", cf. https://gcc.gnu.org/onlinedocs/gcc/Simple-Constraints.html#Simple-Constraints) is not supported on AMD GCN. This causes an ICE during the compilation of gcc.dg/asm-4.c. We should skip the test for the amdgcn-*-* target. Can I merge the patch below into trunk? Best regards, Frederik 2019-12-05 Frederik Harwath <frederik@codesourcery.com> gcc/testsuite/ * gcc.dg/asm-4.c: Skip on target amdgcn-*-*.