From patchwork Fri Nov 2 18:38:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudakshina Das X-Patchwork-Id: 992508 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-488913-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="bQqp6dUw"; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com header.b="XiOj1zNU"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42mrSn0zM6zB4P2 for ; Sat, 3 Nov 2018 05:39:04 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type:mime-version; q=dns; s=default; b=TDB8z4Rj4JanX+abYG4KUFe/5ragZlJRTQ2XGk/MWFJDSoLRBd wtPW+pnCh0FiGe7GAASQaHruvq6IWL8l2QyGjGsj0aLNVkpVRWv2fz5eH+CmmwWW 43W7bZkf5f2wUx3qrPOky09hicrQpTFNHEpN4U5wU4g/WcyCg5S5dRY4o= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type:mime-version; s= default; bh=DcV026zUUl6V7lCX/tdzjFoy7mU=; b=bQqp6dUwpIpj18DHzRyD sJDOmoAzXy57Gfrv6X0GpjRySUWWdIrkg/e8X/nX5uYDH3ccWLN2tyfgh/IAYTYo A6Gw1X6l2vMD0kv8TRbcJpNZVBS/L8Pp4pxqHUw748Xyx2GM13G8A3S+PKqZwir6 gofRIX7MLCaNNBAJsNHeUh8= Received: (qmail 10407 invoked by alias); 2 Nov 2018 18:38:48 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 10128 invoked by uid 89); 2 Nov 2018 18:38:46 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LOTSOFHASH, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.2 spammy=mabi X-HELO: EUR01-DB5-obe.outbound.protection.outlook.com Received: from mail-db5eur01on0062.outbound.protection.outlook.com (HELO EUR01-DB5-obe.outbound.protection.outlook.com) (104.47.2.62) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 02 Nov 2018 18:38:41 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector1-arm-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UydldS1spm1U9ZAGTVesJSejJjinezwKVlJ8TcmfCtE=; b=XiOj1zNUQAo/3BcxEVuunt3p676wt1tNKNGIGFD5bwu1cnvPyk0XqgqmJuBPjx9nqfWATYbAPQTk+/GGPxOKUKb0ggU0G+NmYu7IUNRCipvLJS+HdgT3BQWKfwJ3ZVS2SQQaHq+XfL1Vb5JglWhLkJ48JT5WQ5M+jBzatgIDHOY= Received: from AM5PR0801MB1714.eurprd08.prod.outlook.com (10.169.246.148) by AM5PR0801MB2068.eurprd08.prod.outlook.com (10.168.158.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1294.26; Fri, 2 Nov 2018 18:38:36 +0000 Received: from AM5PR0801MB1714.eurprd08.prod.outlook.com ([fe80::b410:aaa9:dbb9:4e64]) by AM5PR0801MB1714.eurprd08.prod.outlook.com ([fe80::b410:aaa9:dbb9:4e64%7]) with mapi id 15.20.1294.024; Fri, 2 Nov 2018 18:38:36 +0000 From: Sudakshina Das To: "gcc-patches@gcc.gnu.org" CC: nd , James Greenhalgh , Richard Earnshaw , Marcus Shawcroft Subject: [PATCH, GCC, AARCH64, 5/6] Enable BTI : Add new pass for BTI. Date: Fri, 2 Nov 2018 18:38:36 +0000 Message-ID: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Sudi.Das@arm.com; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) MIME-Version: 1.0 X-IsSubscribed: yes Hi This patch is part of a series that enables ARMv8.5-A in GCC and adds Branch Target Identification Mechanism. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) This patch adds a new pass called "bti" which is triggered by the command line argument -mbranch-protection whenever "bti" is turned on. The pass iterates through the instructions and adds appropriated BTI instructions based on the following: * Add a new "BTI C" at the beginning of a function, unless its already protected by a "PACIASP/PACIBSP". We exempt the functions that are only called directly. * Add a new "BTI J" for every target of an indirect jump, jump table targets, non-local goto targets or labels that might be referenced by variables, constant pools, etc (NOTE_INSN_DELETED_LABEL) Since we have already changed the use of indirect tail calls to only x16 and x17, we do not have to use "BTI JC". (check patch 3/6). Bootstrapped and regression tested with aarch64-none-linux-gnu. Added new tests. Is this ok for trunk? Thanks Sudi *** gcc/ChangeLog *** 2018-xx-xx Sudakshina Das Ramana Radhakrishnan * config.gcc (aarch64*-*-*): Add aarch64-bti-insert.o. * gcc/config/aarch64/aarch64.h: Update comment for TRAMPOLINE_SIZE. * config/aarch64/aarch64.c (aarch64_asm_trampoline_template): Update if bti is enabled. * config/aarch64/aarch64-bti-insert.c: New file. * config/aarch64/aarch64-passes.def (INSERT_PASS_BEFORE): Insert bti pass. * config/aarch64/aarch64-protos.h (make_pass_insert_bti): Declare the new bti pass. * config/aarch64/aarch64.md (bti_nop): Define. * config/aarch64/t-aarch64: Add rule for aarch64-bti-insert.o. *** gcc/testsuite/ChangeLog *** 2018-xx-xx Sudakshina Das * gcc.target/aarch64/bti-1.c: New test. * gcc.target/aarch64/bti-2.c: New test. * lib/target-supports.exp (check_effective_target_aarch64_bti_hw): Add new check for BTI hw. diff --git a/gcc/config.gcc b/gcc/config.gcc index b108697cfc7b1c9c6dc1f30cca6fd1158182c29e..3e77f9df6ad6ca55fccca50387eab4b2501af647 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -317,7 +317,7 @@ aarch64*-*-*) c_target_objs="aarch64-c.o" cxx_target_objs="aarch64-c.o" d_target_objs="aarch64-d.o" - extra_objs="aarch64-builtins.o aarch-common.o cortex-a57-fma-steering.o aarch64-speculation.o falkor-tag-collision-avoidance.o" + extra_objs="aarch64-builtins.o aarch-common.o cortex-a57-fma-steering.o aarch64-speculation.o falkor-tag-collision-avoidance.o aarch64-bti-insert.o" target_gtfiles="\$(srcdir)/config/aarch64/aarch64-builtins.c" target_has_targetm_common=yes ;; diff --git a/gcc/config/aarch64/aarch64-bti-insert.c b/gcc/config/aarch64/aarch64-bti-insert.c new file mode 100644 index 0000000000000000000000000000000000000000..efd57620d8803302e03ca643b9f2495e188dc19b --- /dev/null +++ b/gcc/config/aarch64/aarch64-bti-insert.c @@ -0,0 +1,195 @@ +/* Branch Target Identification for AArch64 architecture. + Copyright (C) 2018 Free Software Foundation, Inc. + Contributed by Arm Ltd. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . */ + +#define IN_TARGET_CODE 1 + +#include "config.h" +#define INCLUDE_STRING +#include "system.h" +#include "coretypes.h" +#include "backend.h" +#include "target.h" +#include "rtl.h" +#include "tree.h" +#include "memmodel.h" +#include "gimple.h" +#include "tm_p.h" +#include "stringpool.h" +#include "attribs.h" +#include "emit-rtl.h" +#include "gimplify.h" +#include "gimple-iterator.h" +#include "dumpfile.h" +#include "rtl-iter.h" +#include "cfgrtl.h" +#include "tree-pass.h" +#include "cgraph.h" + +namespace { + +const pass_data pass_data_insert_bti = +{ + RTL_PASS, /* type. */ + "bti", /* name. */ + OPTGROUP_NONE, /* optinfo_flags. */ + TV_MACH_DEP, /* tv_id. */ + 0, /* properties_required. */ + 0, /* properties_provided. */ + 0, /* properties_destroyed. */ + 0, /* todo_flags_start. */ + 0, /* todo_flags_finish. */ +}; + +/* Check if X (or any sub-rtx of X) is a PACIASP/PACIBSP instruction. */ +static bool +aarch64_pac_insn_p (rtx x) +{ + if (!INSN_P (x)) + return x; + + subrtx_var_iterator::array_type array; + FOR_EACH_SUBRTX_VAR (iter, array, PATTERN (x), ALL) + { + rtx sub = *iter; + if (sub && GET_CODE (sub) == UNSPEC) + { + int unspec_val = XINT (sub, 1); + switch (unspec_val) + { + case UNSPEC_PACIASP: + case UNSPEC_PACIBSP: + return true; + + default: + return false; + } + iter.skip_subrtxes (); + } + } + return false; +} + +/* Insert the BTI instruction. */ +/* This is implemented as a late RTL pass that runs before branch + shortening and does the following. */ +static unsigned int +rest_of_insert_bti (void) +{ + timevar_push (TV_MACH_DEP); + + rtx bti_insn; + rtx_insn *insn; + basic_block bb; + + /* Exempt function that are only called directly. */ + if (!cgraph_node::get (cfun->decl)->only_called_directly_p ()) + { + bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb; + insn = BB_HEAD (bb); + if (!aarch64_pac_insn_p (get_first_nonnote_insn ())) + { + bti_insn = gen_bti_nop (GEN_INT (INSN_BTI_C)); + emit_insn_before (bti_insn, insn); + } + } + + bb = 0; + FOR_EACH_BB_FN (bb, cfun) + { + for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); + insn = NEXT_INSN (insn)) + { + if ((LABEL_P (insn) + && (LABEL_PRESERVE_P (insn) + || bb->flags & BB_NON_LOCAL_GOTO_TARGET)) + || (NOTE_P (insn) + && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)) + { + bti_insn = gen_bti_nop (GEN_INT (INSN_BTI_J)); + emit_insn_after (bti_insn, insn); + continue; + } + + if (JUMP_P (insn)) + { + rtx target = JUMP_LABEL (insn); + if (target == NULL_RTX || ANY_RETURN_P (target)) + continue; + + /* Check the jump is a switch table. */ + rtx_insn *label = as_a (target); + rtx_insn *table = next_insn (label); + if (table == NULL_RTX || !JUMP_TABLE_DATA_P (table)) + continue; + + /* For the indirect jump find out all places it jumps and insert + a BTI instruction there. */ + edge_iterator ei; + edge e; + basic_block dest_blk; + + FOR_EACH_EDGE (e, ei, bb->succs) + { + rtx_insn *insn; + + dest_blk = e->dest; + insn = BB_HEAD (dest_blk); + gcc_assert (LABEL_P (insn)); + bti_insn = gen_bti_nop (GEN_INT (INSN_BTI_J)); + emit_insn_after (bti_insn, insn); + } + continue; + } + + } + } + + timevar_pop (TV_MACH_DEP); + return 0; +} + + +class pass_insert_bti : public rtl_opt_pass +{ +public: + pass_insert_bti (gcc::context *ctxt) + : rtl_opt_pass (pass_data_insert_bti, ctxt) + {} + + /* opt_pass methods: */ + virtual bool gate (function *) + { + return aarch64_bti_enabled (); + } + + virtual unsigned int execute (function *) + { + return rest_of_insert_bti (); + } + +}; // class pass_insert_bti + +} // anon namespace + +rtl_opt_pass * +make_pass_insert_bti (gcc::context *ctxt) +{ + return new pass_insert_bti (ctxt); +} diff --git a/gcc/config/aarch64/aarch64-passes.def b/gcc/config/aarch64/aarch64-passes.def index 3982b6ea6290379e6ecac8046ebb27a14d2342f0..d3e316f406ecb0119787a67ad1c62fafaaf99a88 100644 --- a/gcc/config/aarch64/aarch64-passes.def +++ b/gcc/config/aarch64/aarch64-passes.def @@ -21,3 +21,4 @@ INSERT_PASS_AFTER (pass_regrename, 1, pass_fma_steering); INSERT_PASS_BEFORE (pass_reorder_blocks, 1, pass_track_speculation); INSERT_PASS_AFTER (pass_machine_reorg, 1, pass_tag_collision_avoidance); +INSERT_PASS_BEFORE (pass_shorten_branches, 1, pass_insert_bti); diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 913b63efb5eec3c7b600d9fb18b4a6c5e41d1fc5..1767356c5ef2c82d337acc14260d2d38b448a6f2 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -401,6 +401,15 @@ enum aarch64_key_type { extern enum aarch64_key_type aarch64_ra_sign_key; +/* Enum for HINT values for BTI instructions. */ +enum bti_insn_type +{ + INSN_BTI_NOARG = 32, + INSN_BTI_C = 34, + INSN_BTI_J = 36, + INSN_BTI_JC = 38 +}; + extern struct tune_params aarch64_tune_params; void aarch64_post_cfi_startproc (void); @@ -637,6 +646,7 @@ extern void aarch64_d_target_versions (void); rtl_opt_pass *make_pass_fma_steering (gcc::context *); rtl_opt_pass *make_pass_track_speculation (gcc::context *); rtl_opt_pass *make_pass_tag_collision_avoidance (gcc::context *); +rtl_opt_pass *make_pass_insert_bti (gcc::context *ctxt); poly_uint64 aarch64_regmode_natural_size (machine_mode); diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 34938b4271d167873d689cc8e4c2be9a00981434..09d76b5737b552abceba36634594050770f4e6cc 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -924,7 +924,7 @@ typedef struct #define RETURN_ADDR_RTX aarch64_return_addr -/* 3 insns + padding + 2 pointer-sized entries. */ +/* BTI c + 3 insns + 2 pointer-sized entries. */ #define TRAMPOLINE_SIZE (TARGET_ILP32 ? 24 : 32) /* Trampolines contain dwords, so must be dword aligned. */ diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index f60cf9d5b023503013dd0ac3e13e0d0e883a66e3..12a55a640de4fdc5df21d313c7ea6841f1daf3f2 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -8049,18 +8049,33 @@ aarch64_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) static void aarch64_asm_trampoline_template (FILE *f) { + int offset1 = 16; + int offset2 = 20; + + if (aarch64_bti_enabled ()) + { + asm_fprintf (f, "\thint\t34\n"); + offset1 -= 4; + offset2 -= 4; + } + if (TARGET_ILP32) { - asm_fprintf (f, "\tldr\tw%d, .+16\n", IP1_REGNUM - R0_REGNUM); - asm_fprintf (f, "\tldr\tw%d, .+16\n", STATIC_CHAIN_REGNUM - R0_REGNUM); + asm_fprintf (f, "\tldr\tw%d, .+%d\n", IP1_REGNUM - R0_REGNUM, offset1); + asm_fprintf (f, "\tldr\tw%d, .+%d\n", STATIC_CHAIN_REGNUM - R0_REGNUM, + offset1); } else { - asm_fprintf (f, "\tldr\t%s, .+16\n", reg_names [IP1_REGNUM]); - asm_fprintf (f, "\tldr\t%s, .+20\n", reg_names [STATIC_CHAIN_REGNUM]); + asm_fprintf (f, "\tldr\t%s, .+%d\n", reg_names [IP1_REGNUM], offset1); + asm_fprintf (f, "\tldr\t%s, .+%d\n", reg_names [STATIC_CHAIN_REGNUM], + offset2); } asm_fprintf (f, "\tbr\t%s\n", reg_names [IP1_REGNUM]); - assemble_aligned_integer (4, const0_rtx); + + if (!aarch64_bti_enabled ()) + assemble_aligned_integer (4, const0_rtx); + assemble_aligned_integer (POINTER_BYTES, const0_rtx); assemble_aligned_integer (POINTER_BYTES, const0_rtx); } diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 3ca6d61e7e28b780f94bf5080b126dac60fe0524..30693ce83fea1ccc6ee5e4aad1f0f0cd9b44f47a 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -240,6 +240,7 @@ UNSPECV_BLOCKAGE ; Represent a blockage UNSPECV_PROBE_STACK_RANGE ; Represent stack range probing. UNSPECV_SPECULATION_BARRIER ; Represent speculation barrier. + UNSPECV_BTI_NOP ; Represent a BTI instruction. ] ) @@ -6720,6 +6721,40 @@ [(set_attr "type" "csel")] ) +(define_insn "bti_nop" + [(unspec_volatile [(match_operand:SI 0 "const_int_operand")] + UNSPECV_BTI_NOP)] + "" + { + char buf[100]; + bti_insn_type val = (bti_insn_type) INTVAL (operands[0]); + switch (val) + { + case INSN_BTI_NOARG: + snprintf (buf, sizeof (buf), "hint\t%d // %s", val, "bti"); + break; + + case INSN_BTI_C: + snprintf (buf, sizeof (buf), "hint\t%d // %s", val, "bti c"); + break; + + case INSN_BTI_J: + snprintf (buf, sizeof (buf), "hint\t%d // %s", val, "bti j"); + break; + + case INSN_BTI_JC: + snprintf (buf, sizeof (buf), "hint\t%d // %s", val, "bti jc"); + break; + + default: + gcc_unreachable (); + } + output_asm_insn (buf, operands); + return ""; + } + [(set_attr "type" "no_insn")] +) + ;; Helper for aarch64.c code. (define_expand "set_clobber_cc" [(parallel [(set (match_operand 0) diff --git a/gcc/config/aarch64/t-aarch64 b/gcc/config/aarch64/t-aarch64 index e91dccea9954c2c387fb111d1b357dd2c220ff0a..a2048547be56eba8a47c22c9d2b94e787364828f 100644 --- a/gcc/config/aarch64/t-aarch64 +++ b/gcc/config/aarch64/t-aarch64 @@ -91,6 +91,15 @@ falkor-tag-collision-avoidance.o: \ $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ $(srcdir)/config/aarch64/falkor-tag-collision-avoidance.c +aarch64-bti-insert.o: $(srcdir)/config/aarch64/aarch64-bti-insert.c \ + $(CONFIG_H) $(SYSTEM_H) $(TM_H) $(REGS_H) insn-config.h $(RTL_BASE_H) \ + dominance.h cfg.h cfganal.h $(BASIC_BLOCK_H) $(INSN_ATTR_H) $(RECOG_H) \ + output.h hash-map.h $(DF_H) $(OBSTACK_H) $(TARGET_H) $(RTL_H) \ + $(CONTEXT_H) $(TREE_PASS_H) regrename.h \ + $(srcdir)/config/aarch64/aarch64-protos.h + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ + $(srcdir)/config/aarch64/aarch64-bti-insert.c + comma=, MULTILIB_OPTIONS = $(subst $(comma),/, $(patsubst %, mabi=%, $(subst $(comma),$(comma)mabi=,$(TM_MULTILIB_CONFIG)))) MULTILIB_DIRNAMES = $(subst $(comma), ,$(TM_MULTILIB_CONFIG)) diff --git a/gcc/testsuite/gcc.target/aarch64/bti-1.c b/gcc/testsuite/gcc.target/aarch64/bti-1.c new file mode 100644 index 0000000000000000000000000000000000000000..575d01a5411a19dabcdb56b777e5d87d9703a848 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/bti-1.c @@ -0,0 +1,59 @@ +/* { dg-do compile } */ +/* -Os to create jump table. */ +/* { dg-options "-Os -mbranch-protection=standard" } */ + +extern int f1 (void); +extern int f2 (void); +extern int f3 (void); +extern int f4 (void); +extern int f5 (void); +extern int f6 (void); +extern int f7 (void); +extern int f8 (void); +extern int f9 (void); +extern int f10 (void); + +int (*ptr) (void); + +int +f_jump_table (int y, int n) +{ + int i; + for (i = 0; i < n ;i ++) + { + switch (y) + { + case 0 : ptr = f1; break; + case 1 : ptr = f2; break; + case 2 : ptr = f3; break; + case 3 : ptr = f4; break; + case 4 : ptr = f5; break; + case 5 : ptr = f6; break; + case 6 : ptr = f7; break; + case 7 : ptr = f8; break; + case 8 : ptr = f9; break; + case 9 : ptr = f10; break; + default: break; + } + y += ptr (); + } + return (y == 0)? y+1:4; +} +/* f_jump_table should have PACIASP and AUTIASP. */ +/* { dg-final { scan-assembler-times "hint\t25" 1 } } */ +/* { dg-final { scan-assembler-times "hint\t29" 1 } } */ + +int +f_label_address () +{ + static void * addr = &&lab1; + goto *addr; +lab1: + addr = &&lab2; + return 1; +lab2: + addr = &&lab1; + return 2; +} +/* { dg-final { scan-assembler-times "hint\t34" 1 } } */ +/* { dg-final { scan-assembler-times "hint\t36" 12 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/bti-2.c b/gcc/testsuite/gcc.target/aarch64/bti-2.c new file mode 100644 index 0000000000000000000000000000000000000000..e50eef15c8936d00716c582e90b235add5da9136 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/bti-2.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-require-effective-target aarch64_bti_hw } */ +/* { dg-options "-mbranch-protection=standard" } */ + +#include + +typedef int FP (int); + +int +f1 (FP fp, int n) +{ + return (fp) (n); +} + +int +f2 (int n, FP fp) +{ + return (fp) (n); +} + +int __attribute__ ((noinline)) +func (int x) +{ + return x+1; +} + +int main () +{ + int s = 0; + s += f1 (func, 10); + s += f2 (s, func); + printf ("S: %d\n", s); + return !(s == 23); +} diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index fd74c04d092b0e2341b85eefbebb1f0df9423492..65ff16817f5f88255148bb69d7018975465197dc 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -4270,6 +4270,22 @@ proc check_effective_target_arm_neonv2_hw { } { } [add_options_for_arm_neonv2 ""]] } +# ID_AA64PFR1_EL1.BT using bits[3:0] == 1 implies BTI implimented. +proc check_effective_target_aarch64_bti_hw { } { + if { ![istarget aarch64*-*-*] } { + return 0 + } + return [check_runtime aarch64_bti_hw_available { + int + main (void) + { + int a; + asm volatile ("mrs %0, id_aa64pfr1_el1" : "=r" (a)); + return !((a & 0xf) == 1); + } + } "-O2" ] +} + # Return 1 if the target supports the ARMv8.1 Adv.SIMD extension, 0 # otherwise. The test is valid for AArch64 and ARM. Record the command # line options needed.