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a=ed25519-sha256; c=relaxed/relaxed; t=1709649238; s=strato-dkim-0003; d=gjlay.de; h=Subject:To:From:Date:Message-ID:Cc:Date:From:Subject:Sender; bh=IPxbYFKpg+b8newOjbAwiw/CwVsB/67UFV1FcsSRCzY=; b=h70UXE/C7LRAQqx5bTr84J+NNZlmq4Wl1fWmw8n06mvnMmo7OP7QAnaSTBoyJH5ltJ PRGXhrdJSt+gKLfKQ0Aw== X-RZG-AUTH: ":LXoWVUeid/7A29J/hMvvT3koxZnKT7Qq0xotTetVnKkSgcSjpmy9KwoMJ/K0VA==" Received: from [192.168.2.102] by smtp.strato.de (RZmta 50.2.0 DYNA|AUTH) with ESMTPSA id Jdfd10025EXwOoF (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate) for ; Tue, 5 Mar 2024 15:33:58 +0100 (CET) Message-ID: Date: Tue, 5 Mar 2024 15:33:57 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US From: Georg-Johann Lay To: "gcc-patches@gcc.gnu.org" Subject: [patch,avr,applied] Add two RTL peepholes. X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Register alloc may expand a 3-operand arithmetic X = Y o CST as X = CST X o= Y where it may be better to instead: X = Y X o= CST Johann --- AVR: Add two RTL peepholes. Register alloc may expand a 3-operand arithmetic X = Y o CST as X = CST X o= Y where it may be better to instead: X = Y X o= CST because 1) the first insn may use MOVW for "X = Y", and 2) the operation may be more efficient when performed with a constant, for example when ADIW or SBIW can be used, or some bytes of the constant are 0x00 or 0xff. gcc/ * config/avr/avr.md: Add two RTL peepholes for PLUS, IOR and AND in HI, PSI, SI that swap operation order from "X = CST, X o= Y" to "X = Y, X o= CST". diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index 6bdf4682fab..bc8a59c956c 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -932,6 +932,55 @@ (define_peephole2 ; movw_r operands[5] = gen_rtx_REG (HImode, REGNO (operands[3])); }) + +;; Register alloc may expand a 3-operand arithmetic X = Y o CST as +;; X = CST +;; X o= Y +;; where it may be better to instead: +;; X = Y +;; X o= CST +;; because 1) the first insn may use MOVW for "X = Y", and 2) the +;; operation may be more efficient when performed with a constant, +;; for example when ADIW or SBIW can be used, or some bytes of +;; the constant are 0x00 or 0xff. +(define_peephole2 + [(parallel [(set (match_operand:HISI 0 "d_register_operand") + (match_operand:HISI 1 "const_int_operand")) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_dup 0) + (piaop:HISI (match_dup 0) + (match_operand:HISI 2 "register_operand"))) + (clobber (scratch:QI)) + (clobber (reg:CC REG_CC))])] + "! reg_overlap_mentioned_p (operands[0], operands[2])" + [(parallel [(set (match_dup 0) + (match_dup 2)) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_dup 0) + (piaop:HISI (match_dup 0) + (match_dup 1))) + (clobber (scratch:QI)) + (clobber (reg:CC REG_CC))])]) + +;; Same, but just for plus:HI without a scratch:QI. +(define_peephole2 + [(parallel [(set (match_operand:HI 0 "d_register_operand") + (match_operand:HI 1 "const_int_operand")) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_dup 0) + (plus:HI (match_dup 0) + (match_operand:HI 2 "register_operand"))) + (clobber (reg:CC REG_CC))])] + "! reg_overlap_mentioned_p (operands[0], operands[2])" + [(parallel [(set (match_dup 0) + (match_dup 2)) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_dup 0) + (plus:HI (match_dup 0) + (match_dup 1))) + (clobber (reg:CC REG_CC))])]) + + ;; For LPM loads from AS1 we split ;; R = *Z ;; to @@ -1644,9 +1693,9 @@ (define_insn_and_split "*addhi3_sp" [(set_attr "length" "6") (set_attr "adjust_len" "addto_sp")]) -;; "*addhi3" -;; "*addhq3" "*adduhq3" -;; "*addha3" "*adduha3" +;; "*addhi3_split" +;; "*addhq3_split" "*adduhq3_split" +;; "*addha3_split" "*adduha3_split" (define_insn_and_split "*add3_split" [(set (match_operand:ALL2 0 "register_operand" "=??r,d,!w ,d") (plus:ALL2 (match_operand:ALL2 1 "register_operand" "%0,0,0 ,0") @@ -1661,6 +1710,9 @@ (define_insn_and_split "*add3_split" "" [(set_attr "isa" "*,*,adiw,*")]) +;; "*addhi3" +;; "*addhq3" "*adduhq3" +;; "*addha3" "*adduha3" (define_insn "*add3" [(set (match_operand:ALL2 0 "register_operand" "=??r,d,!w ,d") (plus:ALL2 (match_operand:ALL2 1 "register_operand" "%0,0,0 ,0") @@ -1732,6 +1784,9 @@ (define_insn_and_split "add3_clobber" (clobber (match_dup 3)) (clobber (reg:CC REG_CC))])]) +;; "*addhi3_clobber" +;; "*addhq3_clobber" "*adduhq3_clobber" +;; "*addha3_clobber" "*adduha3_clobber" (define_insn "*add3_clobber" [(set (match_operand:ALL2 0 "register_operand" "=!w ,d ,r") (plus:ALL2 (match_operand:ALL2 1 "register_operand" "%0 ,0 ,0")