From patchwork Tue Jul 23 06:28:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Kewen.Lin" X-Patchwork-Id: 1135425 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-505511-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="CkKDXX7Z"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45t7q53BGCz9sBF for ; Tue, 23 Jul 2019 16:29:03 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:cc:references:from:date:mime-version:in-reply-to :content-type:message-id; q=dns; s=default; b=GBKIMl0VTEgpQCYu5x NtNwLhe99aGLzWY7sc1IZA0u+fCyuC6t0KH81zQi+2w2nrH/g9wv//ksXwKTfRUq w4MAEu0ABxZxqkQVAg+YiNw8zxa6qlQxuhXowqhMLWUD1ADRz0r0TQpMwX9/M/P+ 9jT78JNUNSUVhEdHAXhIiOmqs= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:cc:references:from:date:mime-version:in-reply-to :content-type:message-id; s=default; bh=6DYxOk0+f0vwFaUNN0XdYHOI LYg=; b=CkKDXX7ZxLQIfyStm8Q5jiEm+BwFBKArqjhfbLybKAtRhDThmApI0VlD 87GTLdHE44jfaupPkfbp09Zk8Ueon0C5SC11m5konziNgL7sWZO6h+AQGyJSqqUE LeMphB4PRW5xpf/HeXcabHAkF3MV+xvr86WoLNpTgHrxM+oFmSI= Received: (qmail 94557 invoked by alias); 23 Jul 2019 06:28:54 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 94542 invoked by uid 89); 23 Jul 2019 06:28:54 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-21.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 23 Jul 2019 06:28:52 +0000 Received: from pps.filterd (m0098404.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x6N6RsCo105696 for ; Tue, 23 Jul 2019 02:28:50 -0400 Received: from e06smtp02.uk.ibm.com (e06smtp02.uk.ibm.com [195.75.94.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 2twsr6x9as-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 23 Jul 2019 02:28:49 -0400 Received: from localhost by e06smtp02.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 23 Jul 2019 07:28:44 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x6N6ST7I13959474 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 23 Jul 2019 06:28:29 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E37765204F; Tue, 23 Jul 2019 06:28:43 +0000 (GMT) Received: from 192.168.10.100 (unknown [9.197.230.181]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 5F9825204E; Tue, 23 Jul 2019 06:28:39 +0000 (GMT) Subject: [PATCH V2, rs6000] Support vrotr3 for int vector types To: Segher Boessenkool Cc: GCC Patches , Jakub Jelinek , Richard Biener , richard.sandiford@arm.com, Bill Schmidt References: <232a38b1-76c2-476d-1be0-a1958e5624bb@linux.ibm.com> <20190715085929.GO2125@tucnak> <32f89c4f-cd2d-a7bd-16d2-26fed6bb5f56@linux.ibm.com> <27be90e6-4beb-5c4c-a163-9b136490d783@linux.ibm.com> <20190717134025.GJ20882@gate.crashing.org> <83f8448e-3c59-8991-2176-729d87e08a86@linux.ibm.com> <20190718194818.GT20882@gate.crashing.org> <20190719150647.GZ20882@gate.crashing.org> From: "Kewen.Lin" Date: Tue, 23 Jul 2019 14:28:28 +0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.14; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20190719150647.GZ20882@gate.crashing.org> x-cbid: 19072306-0008-0000-0000-000002FFF5F7 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19072306-0009-0000-0000-0000226D8163 Message-Id: X-IsSubscribed: yes Hi Segher, Thanks for the clarification! Compared with the previous one, this add vrl_and define_insn(s) for explicit AND (truncation) as Jakub's suggestion. Bootstrapped and regtested on powerpc64le-unknown-linux-gnu, is it ok for trunk? Thanks, Kewen ---------------- gcc/ChangeLog 2019-07-23 Kewen Lin * config/rs6000/predicates.md (vint_reg_or_const_vector): New predicate. * config/rs6000/vector.md (vrotr3): New define_expand. * config/rs6000/altivec.md (vrl_and): New define_insns. gcc/testsuite/ChangeLog 2019-07-23 Kewen Lin * gcc.target/powerpc/vec_rotate-1.c: New test. * gcc.target/powerpc/vec_rotate-2.c: New test. on 2019/7/19 下午11:06, Segher Boessenkool wrote: > Hi! > > On Fri, Jul 19, 2019 at 10:21:06AM +0800, Kewen.Lin wrote: >> on 2019/7/19 上午3:48, Segher Boessenkool wrote: >>> On Thu, Jul 18, 2019 at 01:44:36PM +0800, Kewen.Lin wrote: >>>> on 2019/7/17 下午9:40, Segher Boessenkool wrote: >>>>> On Wed, Jul 17, 2019 at 04:32:15PM +0800, Kewen.Lin wrote: >>>>>> Regression testing just launched, is it OK for trunk if it's bootstrapped >>>>>> and regresstested on powerpc64le-unknown-linux-gnu? >>>>> >>>>>> +;; Expanders for rotatert to make use of vrotl >>>>>> +(define_expand "vrotr3" >>>>>> + [(set (match_operand:VEC_I 0 "vint_operand") >>>>>> + (rotatert:VEC_I (match_operand:VEC_I 1 "vint_operand") >>>>>> + (match_operand:VEC_I 2 "vint_reg_or_const_vector")))] >>>>> >>>>> Having any rotatert in a define_expand or define_insn will regress. > > This is wrong. I don't know why I thought this for a while. > > There shouldn't be any rotatert in anything that goes through recog, but > that is everything *except* define_expand. So define_insn, define_split, > define_peephole, define_peephole2 (and define_insn_and_split, which is > just syntactic sugar). > >> Thanks for further explanation! Sorry that, but I didn't find this >> HAVE_rotatert definition. I guess it's due to the preparation is always >> "DONE"? Then it doesn't really generate rotatert. > > You only had one in a define_expand. That is fine, that pattern is never > recognised against. HAVE_rotatert means that something somewhere will > recognise rotatert RTL insns; if it isn't set, it doesn't make sense to > ever create them, because they will never match. > >> although I can see rotatert in insn like below, it seems fine in note? > > Sure, many things are allowed in notes that can never show up in RTL > proper. > > So, this approach will work fine, and not be too bad. Could you do a > new patch with it? It's simple to do, and even if the generic thing > will happen eventually, this is a nice stepping stone for that. > > Thanks, and sorry for the confusion, > > > Segher > diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index b6a22d9010c..2b6a957d4a6 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -1666,6 +1666,60 @@ "vrl %0,%1,%2" [(set_attr "type" "vecsimple")]) +;; Here these vrl_and are for vrotr3 expansion. +;; since SHIFT_COUNT_TRUNCATED is set as zero, to append one explicit +;; AND to indicate truncation but emit vrl insn. +(define_insn "vrlv2di_and" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (and:V2DI + (rotate:V2DI (match_operand:V2DI 1 "register_operand" "v") + (match_operand:V2DI 2 "register_operand" "v")) + (const_vector:V2DI [(const_int 63) (const_int 63)])))] + "VECTOR_UNIT_P8_VECTOR_P (V2DImode)" + "vrld %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "vrlv4si_and" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (and:V4SI + (rotate:V4SI (match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")) + (const_vector:V4SI [(const_int 31) (const_int 31) + (const_int 31) (const_int 31)])))] + "VECTOR_UNIT_ALTIVEC_P (V4SImode)" + "vrlw %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "vrlv8hi_and" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (and:V8HI + (rotate:V8HI (match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")) + (const_vector:V8HI [(const_int 15) (const_int 15) + (const_int 15) (const_int 15) + (const_int 15) (const_int 15) + (const_int 15) (const_int 15)])))] + "VECTOR_UNIT_ALTIVEC_P (V8HImode)" + "vrlh %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "vrlv16qi_and" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (and:V16QI + (rotate:V16QI (match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")) + (const_vector:V16QI [(const_int 7) (const_int 7) + (const_int 7) (const_int 7) + (const_int 7) (const_int 7) + (const_int 7) (const_int 7) + (const_int 7) (const_int 7) + (const_int 7) (const_int 7) + (const_int 7) (const_int 7) + (const_int 7) (const_int 7)])))] + "VECTOR_UNIT_ALTIVEC_P (V16QImode)" + "vrlb %0,%1,%2" + [(set_attr "type" "vecsimple")]) + (define_insn "altivec_vrlmi" [(set (match_operand:VIlong 0 "register_operand" "=v") (unspec:VIlong [(match_operand:VIlong 1 "register_operand" "0") diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 8ca98299950..c4c74630d26 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -163,6 +163,17 @@ return VINT_REGNO_P (REGNO (op)); }) +;; Return 1 if op is a vector register that operates on integer vectors +;; or if op is a const vector with integer vector modes. +(define_predicate "vint_reg_or_const_vector" + (match_code "reg,subreg,const_vector") +{ + if (GET_CODE (op) == CONST_VECTOR && GET_MODE_CLASS (mode) == MODE_VECTOR_INT) + return 1; + + return vint_operand (op, mode); +}) + ;; Return 1 if op is a vector register to do logical operations on (and, or, ;; xor, etc.) (define_predicate "vlogical_operand" diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index 70bcfe02e22..b53f9717eb2 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -1260,6 +1260,35 @@ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" "") +;; Expanders for rotatert to make use of vrotl +(define_expand "vrotr3" + [(set (match_operand:VEC_I 0 "vint_operand") + (rotatert:VEC_I (match_operand:VEC_I 1 "vint_operand") + (match_operand:VEC_I 2 "vint_reg_or_const_vector")))] + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" +{ + rtx rot_count = gen_reg_rtx (mode); + if (GET_CODE (operands[2]) == CONST_VECTOR) + { + machine_mode inner_mode = GET_MODE_INNER (mode); + unsigned int bits = GET_MODE_PRECISION (inner_mode); + rtx mask_vec = gen_const_vec_duplicate (mode, GEN_INT (bits - 1)); + rtx imm_vec + = simplify_const_unary_operation (NEG, mode, operands[2], + GET_MODE (operands[2])); + imm_vec + = simplify_const_binary_operation (AND, mode, imm_vec, mask_vec); + rot_count = force_reg (mode, imm_vec); + emit_insn (gen_vrotl3 (operands[0], operands[1], rot_count)); + } + else + { + emit_insn (gen_neg2 (rot_count, operands[2])); + emit_insn (gen_vrl_and (operands[0], operands[1], rot_count)); + } + DONE; +}) + ;; Expanders for arithmetic shift left on each vector element (define_expand "vashl3" [(set (match_operand:VEC_I 0 "vint_operand") diff --git a/gcc/testsuite/gcc.target/powerpc/vec_rotate-1.c b/gcc/testsuite/gcc.target/powerpc/vec_rotate-1.c new file mode 100644 index 00000000000..80aca1a94a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec_rotate-1.c @@ -0,0 +1,46 @@ +/* { dg-options "-O3" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ + +/* Check vectorizer can exploit vector rotation instructions on Power, mainly + for the case rotation count is const number. */ + +#define N 256 +unsigned long long sud[N], rud[N]; +unsigned int suw[N], ruw[N]; +unsigned short suh[N], ruh[N]; +unsigned char sub[N], rub[N]; + +void +testULL () +{ + for (int i = 0; i < 256; ++i) + rud[i] = (sud[i] >> 8) | (sud[i] << (sizeof (sud[0]) * 8 - 8)); +} + +void +testUW () +{ + for (int i = 0; i < 256; ++i) + ruw[i] = (suw[i] >> 8) | (suw[i] << (sizeof (suw[0]) * 8 - 8)); +} + +void +testUH () +{ + for (int i = 0; i < 256; ++i) + ruh[i] = (unsigned short) (suh[i] >> 9) + | (unsigned short) (suh[i] << (sizeof (suh[0]) * 8 - 9)); +} + +void +testUB () +{ + for (int i = 0; i < 256; ++i) + rub[i] = (unsigned char) (sub[i] >> 5) + | (unsigned char) (sub[i] << (sizeof (sub[0]) * 8 - 5)); +} + +/* { dg-final { scan-assembler {\mvrld\M} } } */ +/* { dg-final { scan-assembler {\mvrlw\M} } } */ +/* { dg-final { scan-assembler {\mvrlh\M} } } */ +/* { dg-final { scan-assembler {\mvrlb\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec_rotate-2.c b/gcc/testsuite/gcc.target/powerpc/vec_rotate-2.c new file mode 100644 index 00000000000..affda6c023b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec_rotate-2.c @@ -0,0 +1,47 @@ +/* { dg-options "-O3" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ + +/* Check vectorizer can exploit vector rotation instructions on Power, mainly + for the case rotation count isn't const number. */ + +#define N 256 +unsigned long long sud[N], rud[N]; +unsigned int suw[N], ruw[N]; +unsigned short suh[N], ruh[N]; +unsigned char sub[N], rub[N]; +extern unsigned char rot_cnt; + +void +testULL () +{ + for (int i = 0; i < 256; ++i) + rud[i] = (sud[i] >> rot_cnt) | (sud[i] << (sizeof (sud[0]) * 8 - rot_cnt)); +} + +void +testUW () +{ + for (int i = 0; i < 256; ++i) + ruw[i] = (suw[i] >> rot_cnt) | (suw[i] << (sizeof (suw[0]) * 8 - rot_cnt)); +} + +void +testUH () +{ + for (int i = 0; i < 256; ++i) + ruh[i] = (unsigned short) (suh[i] >> rot_cnt) + | (unsigned short) (suh[i] << (sizeof (suh[0]) * 8 - rot_cnt)); +} + +void +testUB () +{ + for (int i = 0; i < 256; ++i) + rub[i] = (unsigned char) (sub[i] >> rot_cnt) + | (unsigned char) (sub[i] << (sizeof (sub[0]) * 8 - rot_cnt)); +} + +/* { dg-final { scan-assembler {\mvrld\M} } } */ +/* { dg-final { scan-assembler {\mvrlw\M} } } */ +/* { dg-final { scan-assembler {\mvrlh\M} } } */ +/* { dg-final { scan-assembler {\mvrlb\M} } } */