diff mbox series

[committed] amdgcn: Add cond_add/sub/and/ior/xor for all vector modes

Message ID f0b7088c-3329-40e7-3632-f94543ac570b@codesourcery.com
State New
Headers show
Series [committed] amdgcn: Add cond_add/sub/and/ior/xor for all vector modes | expand

Commit Message

Andrew Stubbs March 18, 2020, 1 p.m. UTC 
This patch adds support for new conditional vector operators, including 
cond_mult, and more modes for cond_add, cond_sub, cond_and, cond_ior and 
cond_xor. This allows vectorization of more algorithms and several new 
test passes.

The min and max operators remain on the to do list because those require 
extends and truncates for some modes.

Andrew
diff mbox series

Patch

amdgcn: Add cond_add/sub/and/ior/xor for all vector modes

2020-03-18  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config/gcn/gcn-valu.md (COND_MODE): Delete.
	(COND_INT_MODE): Delete.
	(cond_op): Add "mult".
	(cond_<expander><mode>): Use VEC_ALLREG_MODE.
	(cond_<expander><mode>): Use VEC_ALLREG_INT_MODE.

diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index a8034f77798..68d89fadc9e 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -2903,19 +2903,15 @@ 
     DONE;
   })
 
-; FIXME this should be VEC_REG_MODE, but not all dependencies are implemented.
-(define_mode_iterator COND_MODE [V64SI V64DI V64SF V64DF])
-(define_mode_iterator COND_INT_MODE [V64SI V64DI])
-
-(define_code_iterator cond_op [plus minus])
+(define_code_iterator cond_op [plus minus mult])
 
 (define_expand "cond_<expander><mode>"
-  [(match_operand:COND_MODE 0 "register_operand")
+  [(match_operand:VEC_ALLREG_MODE 0 "register_operand")
    (match_operand:DI 1 "register_operand")
-   (cond_op:COND_MODE
-     (match_operand:COND_MODE 2 "gcn_alu_operand")
-     (match_operand:COND_MODE 3 "gcn_alu_operand"))
-   (match_operand:COND_MODE 4 "register_operand")]
+   (cond_op:VEC_ALLREG_MODE
+     (match_operand:VEC_ALLREG_MODE 2 "gcn_alu_operand")
+     (match_operand:VEC_ALLREG_MODE 3 "gcn_alu_operand"))
+   (match_operand:VEC_ALLREG_MODE 4 "register_operand")]
   ""
   {
     operands[1] = force_reg (DImode, operands[1]);
@@ -2927,15 +2923,16 @@ 
     DONE;
   })
 
+;; TODO smin umin smax umax
 (define_code_iterator cond_bitop [and ior xor])
 
 (define_expand "cond_<expander><mode>"
-  [(match_operand:COND_INT_MODE 0 "register_operand")
+  [(match_operand:VEC_ALLREG_INT_MODE 0 "register_operand")
    (match_operand:DI 1 "register_operand")
-   (cond_bitop:COND_INT_MODE
-     (match_operand:COND_INT_MODE 2 "gcn_alu_operand")
-     (match_operand:COND_INT_MODE 3 "gcn_alu_operand"))
-   (match_operand:COND_INT_MODE 4 "register_operand")]
+   (cond_bitop:VEC_ALLREG_INT_MODE
+     (match_operand:VEC_ALLREG_INT_MODE 2 "gcn_alu_operand")
+     (match_operand:VEC_ALLREG_INT_MODE 3 "gcn_alu_operand"))
+   (match_operand:VEC_ALLREG_INT_MODE 4 "register_operand")]
   ""
   {
     operands[1] = force_reg (DImode, operands[1]);