diff mbox series

rs6000: Add "enabled" attribute

Message ID e7756074f2cf71c6bc1eb54672c8f61773e75785.1558127690.git.segher@kernel.crashing.org
State New
Headers show
Series rs6000: Add "enabled" attribute | expand

Commit Message

Segher Boessenkool May 17, 2019, 9:24 p.m. UTC 
This adds the "enabled" attribute to the rs6000 backend.  It uses the
(new) "isa" attribute to automatically select which instruction
alternatives should be enabled.

For now it allows isa strings of "p5", "p6", "p7", meaning the
instructions introduced on that CPU, not requiring vectors; and "p7v",
"p8v", "p9v" for the same, but with vectors.

These are currently mapped to TARGET_POPCNTB, TARGET_CMPB,
TARGET_POPCNTD, TARGET_VSX, TARGET_P8_VECTOR, and TARGET_P9_VECTOR;
that will change to something a bit saner later.

This patch does not use those attributes anywhere yet.  Committing
to trunk.


Segher


2019-05-17  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/rs6000.md (isa): New attribute.
	(enabled): New attribute.

---
 gcc/config/rs6000/rs6000.md | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)
diff mbox series

Patch

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 31fc90a..0906ccb 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -265,6 +265,39 @@  (define_attr "cpu"
    rs64a,mpccore,cell,ppca2,titan"
   (const (symbol_ref "(enum attr_cpu) rs6000_tune")))
 
+;; The ISA we implement.
+(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9v" (const_string "any"))
+
+;; Is this alternative enabled for the current CPU/ISA/etc.?
+(define_attr "enabled" ""
+  (cond
+    [(eq_attr "isa" "any")
+     (const_int 1)
+
+     (and (eq_attr "isa" "p5")
+	  (match_test "TARGET_POPCNTB"))
+     (const_int 1)
+
+     (and (eq_attr "isa" "p6")
+	  (match_test "TARGET_CMPB"))
+     (const_int 1)
+
+     (and (eq_attr "isa" "p7")
+	  (match_test "TARGET_POPCNTD"))
+     (const_int 1)
+
+     (and (eq_attr "isa" "p7v")
+	  (match_test "TARGET_VSX"))
+     (const_int 1)
+
+     (and (eq_attr "isa" "p8v")
+	  (match_test "TARGET_P8_VECTOR"))
+     (const_int 1)
+
+     (and (eq_attr "isa" "p9v")
+	  (match_test "TARGET_P9_VECTOR"))
+     (const_int 1)
+    ] (const_int 0)))
 
 ;; If this instruction is microcoded on the CELL processor
 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded