@@ -114,7 +114,7 @@ (define_insn_reservation "ppc403-jmpreg" 1
"bpu_40x")
(define_insn_reservation "ppc403-cr" 2
- (and (eq_attr "type" "cr_logical,delayed_cr")
+ (and (eq_attr "type" "cr_logical")
(eq_attr "cpu" "ppc403,ppc405"))
"bpu_40x")
@@ -95,7 +95,7 @@ (define_insn_reservation "ppc440-branch" 1
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-compare" 2
- (and (ior (eq_attr "type" "cmp,cr_logical,delayed_cr,mfcr")
+ (and (ior (eq_attr "type" "cmp,cr_logical,mfcr")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc440"))
@@ -71,7 +71,7 @@ (define_insn_reservation "ppc476-simple-integer" 1
ppc476_i_pipe|ppc476_lj_pipe")
(define_insn_reservation "ppc476-complex-integer" 1
- (and (eq_attr "type" "cmp,cr_logical,delayed_cr,cntlz,isel,isync,sync,trap,popcnt")
+ (and (eq_attr "type" "cmp,cr_logical,cntlz,isel,isync,sync,trap,popcnt")
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_i_pipe")
@@ -116,7 +116,7 @@ (define_insn_reservation "ppc601-mtcr" 4
"iu_ppc601,bpu_ppc601")
(define_insn_reservation "ppc601-crlogical" 4
- (and (eq_attr "type" "cr_logical,delayed_cr")
+ (and (eq_attr "type" "cr_logical")
(eq_attr "cpu" "ppc601"))
"bpu_ppc601")
@@ -126,7 +126,7 @@ (define_insn_reservation "ppc603-ddiv" 33
"fpu_603*33")
(define_insn_reservation "ppc603-crlogical" 2
- (and (eq_attr "type" "cr_logical,delayed_cr,mfcr,mtcr")
+ (and (eq_attr "type" "cr_logical,mfcr,mtcr")
(eq_attr "cpu" "ppc603"))
"sru_603")
@@ -233,12 +233,12 @@ (define_insn_reservation "ppc604-mtcr" 2
"iu1_6xx|iu2_6xx")
(define_insn_reservation "ppc604-crlogical" 2
- (and (eq_attr "type" "cr_logical,delayed_cr")
+ (and (eq_attr "type" "cr_logical")
(eq_attr "cpu" "ppc604"))
"bpu_6xx")
(define_insn_reservation "ppc604e-crlogical" 2
- (and (eq_attr "type" "cr_logical,delayed_cr")
+ (and (eq_attr "type" "cr_logical")
(eq_attr "cpu" "ppc604e,ppc620,ppc630"))
"cru_6xx")
@@ -141,7 +141,7 @@ (define_insn_reservation "ppc7450-mfcr" 2
"ppc7450_du,mciu_7450")
(define_insn_reservation "ppc7450-crlogical" 1
- (and (eq_attr "type" "cr_logical,delayed_cr")
+ (and (eq_attr "type" "cr_logical")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,mciu_7450")
@@ -144,7 +144,7 @@ (define_insn_reservation "ppc750-mfcr" 2
"ppc750_du,iu1_7xx")
(define_insn_reservation "ppc750-crlogical" 3
- (and (eq_attr "type" "cr_logical,delayed_cr")
+ (and (eq_attr "type" "cr_logical")
(eq_attr "cpu" "ppc750,ppc7400"))
"nothing,sru_7xx*2")
@@ -127,7 +127,7 @@ (define_insn_reservation "ppc8540_divide" 14
;; CR logical
(define_insn_reservation "ppc8540_cr_logical" 1
- (and (eq_attr "type" "cr_logical,delayed_cr")
+ (and (eq_attr "type" "cr_logical")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_bu,ppc8540_retire")
@@ -288,7 +288,7 @@ (define_insn_reservation "cell-branchreg" 1
;; page 90, special cases for CR hazard, only one instr can access cr per cycle
;; if insn reads CR following a stwcx, pipeline stall till stwcx finish
(define_insn_reservation "cell-crlogical" 1
- (and (eq_attr "type" "cr_logical,delayed_cr")
+ (and (eq_attr "type" "cr_logical")
(eq_attr "cpu" "cell"))
"bru_cell+slot01")
@@ -121,7 +121,7 @@ (define_insn_reservation "ppce300c3_divide" 20
;; CR logical
(define_insn_reservation "ppce300c3_cr_logical" 1
- (and (eq_attr "type" "cr_logical,delayed_cr")
+ (and (eq_attr "type" "cr_logical")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
@@ -110,7 +110,7 @@ (define_insn_reservation "e500mc_branch" 1
;; CR logical.
(define_insn_reservation "e500mc_cr_logical" 1
- (and (eq_attr "type" "cr_logical,delayed_cr")
+ (and (eq_attr "type" "cr_logical")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_bu,e500mc_retire")
@@ -129,7 +129,7 @@ (define_insn_reservation "e500mc64_branch" 1
;; CR logical.
(define_insn_reservation "e500mc64_cr_logical" 1
- (and (eq_attr "type" "cr_logical,delayed_cr")
+ (and (eq_attr "type" "cr_logical")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_bu,e500mc64_retire")
@@ -185,6 +185,6 @@ (define_insn_reservation "e5500_branch" 1
;; BU - CR logical.
(define_insn_reservation "e5500_cr_logical" 1
- (and (eq_attr "type" "cr_logical,delayed_cr")
+ (and (eq_attr "type" "cr_logical")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_bu")
@@ -199,7 +199,7 @@ (define_insn_reservation "e6500_branch" 1
;; BU - CR logical.
(define_insn_reservation "e6500_cr_logical" 1
- (and (eq_attr "type" "cr_logical,delayed_cr")
+ (and (eq_attr "type" "cr_logical")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_bu")
@@ -106,7 +106,7 @@ (define_insn_reservation "mpccore-mtjmpr" 4
"bpu_mpc")
(define_insn_reservation "mpccore-jmpreg" 1
- (and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr,mfcr,mtcr,isync")
+ (and (eq_attr "type" "jmpreg,branch,cr_logical,mfcr,mtcr,isync")
(eq_attr "cpu" "mpccore"))
"bpu_mpc")
@@ -351,11 +351,13 @@ (define_insn_reservation "power4-branch" 2
; Condition Register logical ops are split if non-destructive (RT != RB)
(define_insn_reservation "power4-crlogical" 2
(and (eq_attr "type" "cr_logical")
+ (eq_attr "cr_logical_3op" "no")
(eq_attr "cpu" "power4"))
"du1_power4,cru_power4")
(define_insn_reservation "power4-delayedcr" 4
- (and (eq_attr "type" "delayed_cr")
+ (and (eq_attr "type" "cr_logical")
+ (eq_attr "cr_logical_3op" "yes")
(eq_attr "cpu" "power4"))
"du1_power4+du2_power4,cru_power4,cru_power4")
@@ -292,11 +292,13 @@ (define_insn_reservation "power5-branch" 2
; Condition Register logical ops are split if non-destructive (RT != RB)
(define_insn_reservation "power5-crlogical" 2
(and (eq_attr "type" "cr_logical")
+ (eq_attr "cr_logical_3op" "no")
(eq_attr "cpu" "power5"))
"du1_power5,cru_power5")
(define_insn_reservation "power5-delayedcr" 4
- (and (eq_attr "type" "delayed_cr")
+ (and (eq_attr "type" "cr_logical")
+ (eq_attr "cr_logical_3op" "yes")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,cru_power5,cru_power5")
@@ -475,11 +475,6 @@ (define_insn_reservation "power6-crlogical" 3
(define_bypass 3 "power6-crlogical" "power6-branch")
-(define_insn_reservation "power6-delayedcr" 3
- (and (eq_attr "type" "delayed_cr")
- (eq_attr "cpu" "power6"))
- "BRU_power6")
-
(define_insn_reservation "power6-mfcr" 6 ; N/A
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "power6"))
@@ -208,7 +208,7 @@ (define_insn_reservation "power7-compare" 2
(eq_attr "cpu" "power7"))
"DU2F_power7,FXU_power7,FXU_power7")
-(define_bypass 3 "power7-cmp,power7-compare" "power7-crlogical,power7-delayedcr")
+(define_bypass 3 "power7-cmp,power7-compare" "power7-crlogical")
(define_insn_reservation "power7-mul" 4
(and (eq_attr "type" "mul")
@@ -256,11 +256,6 @@ (define_insn_reservation "power7-crlogical" 3
(eq_attr "cpu" "power7"))
"du1_power7,cru_power7")
-(define_insn_reservation "power7-delayedcr" 3
- (and (eq_attr "type" "delayed_cr")
- (eq_attr "cpu" "power7"))
- "du1_power7,cru_power7")
-
(define_insn_reservation "power7-mfcr" 6
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "power7"))
@@ -281,7 +281,7 @@ (define_insn_reservation "power8-mfjmpr" 5
"DU_first_power8,cru_power8+FXU_power8")
(define_insn_reservation "power8-crlogical" 3
- (and (eq_attr "type" "cr_logical,delayed_cr")
+ (and (eq_attr "type" "cr_logical")
(eq_attr "cpu" "power8"))
"DU_first_power8,cru_power8")
@@ -336,7 +336,7 @@ (define_insn_reservation "power9-ldiv" 24
"DU_even_power9,fx_div0_power9*8|fx_div1_power9*8")
(define_insn_reservation "power9-crlogical" 2
- (and (eq_attr "type" "cr_logical,delayed_cr")
+ (and (eq_attr "type" "cr_logical")
(eq_attr "cpu" "power9"))
"DU_any_power9,VSU_power9")
@@ -30706,7 +30706,6 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
case TYPE_CMP:
case TYPE_FPCOMPARE:
case TYPE_CR_LOGICAL:
- case TYPE_DELAYED_CR:
return cost + 2;
case TYPE_EXTS:
case TYPE_MUL:
@@ -31002,7 +31001,8 @@ is_cracked_insn (rtx_insn *insn)
&& get_attr_indexed (insn) == INDEXED_NO)
|| ((type == TYPE_FPLOAD || type == TYPE_FPSTORE)
&& get_attr_update (insn) == UPDATE_YES)
- || type == TYPE_DELAYED_CR
+ || (type == TYPE_CR_LOGICAL
+ && get_attr_cr_logical_3op (insn) == CR_LOGICAL_3OP_YES)
|| (type == TYPE_EXTS
&& get_attr_dot (insn) == DOT_YES)
|| (type == TYPE_SHIFT
@@ -31993,7 +31993,6 @@ insn_must_be_first_in_group (rtx_insn *insn)
case TYPE_MFCR:
case TYPE_MFCRF:
case TYPE_MTCR:
- case TYPE_DELAYED_CR:
case TYPE_CR_LOGICAL:
case TYPE_MTJMPR:
case TYPE_MFJMPR:
@@ -32096,7 +32095,6 @@ insn_must_be_first_in_group (rtx_insn *insn)
switch (type)
{
case TYPE_CR_LOGICAL:
- case TYPE_DELAYED_CR:
case TYPE_MFCR:
case TYPE_MFCRF:
case TYPE_MTCR:
@@ -182,7 +182,7 @@ (define_attr "type"
load,store,fpload,fpstore,vecload,vecstore,
cmp,
branch,jmpreg,mfjmpr,mtjmpr,trap,isync,sync,load_l,store_c,
- cr_logical,delayed_cr,mfcr,mfcrf,mtcr,
+ cr_logical,mfcr,mfcrf,mtcr,
fpcompare,fp,fpsimple,dmul,qmul,sdiv,ddiv,ssqrt,dsqrt,
vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,
vecfloat,vecfdiv,vecdouble,mffgpr,mftgpr,crypto,
@@ -206,6 +206,9 @@ (define_attr "dot" "no,yes" (const_string "no"))
;; This is used for load insns.
(define_attr "sign_extend" "no,yes" (const_string "no"))
+;; Does this cr_logical instruction have three operands? That is, BT != BB.
+(define_attr "cr_logical_3op" "no,yes" (const_string "no"))
+
;; Does this instruction use indexed (that is, reg+reg) addressing?
;; This is used for load and store insns. If operand 0 or 1 is a MEM
;; it is automatically set based on that. If a load or store instruction
@@ -12293,7 +12296,8 @@ (define_insn "cceq_ior_compare"
(const_int 1)))]
""
"cr%q1 %E0,%j2,%j4"
- [(set_attr "type" "cr_logical,delayed_cr")])
+ [(set_attr "type" "cr_logical")
+ (set_attr "cr_logical_3op" "no,yes")])
; Why is the constant -1 here, but 1 in the previous pattern?
; Because ~1 has all but the low bit set.
@@ -12313,7 +12317,8 @@ (define_insn "cceq_ior_compare_complement"
(const_int -1)))]
""
"cr%q1 %E0,%j2,%j4"
- [(set_attr "type" "cr_logical,delayed_cr")])
+ [(set_attr "type" "cr_logical")
+ (set_attr "cr_logical_3op" "no,yes")])
(define_insn "*cceq_rev_compare"
[(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
@@ -12325,7 +12330,8 @@ (define_insn "*cceq_rev_compare"
(const_int 0)))]
""
"crnot %E0,%j1"
- [(set_attr "type" "cr_logical,delayed_cr")])
+ [(set_attr "type" "cr_logical")
+ (set_attr "cr_logical_3op" "no,yes")])
;; If we are comparing the result of two comparisons, this can be done
;; using creqv or crxor.
@@ -146,7 +146,7 @@ (define_insn_reservation "rs64a-mfjmpr" 2
"lsu_rs64")
(define_insn_reservation "rs64a-jmpreg" 1
- (and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr")
+ (and (eq_attr "type" "jmpreg,branch,cr_logical")
(eq_attr "cpu" "rs64a"))
"bpu_rs64")
@@ -85,7 +85,7 @@ (define_insn_reservation "titan_fxu_alu" 1
(define_cpu_unit "titan_bpu_sh" "titan_bpu")
(define_insn_reservation "titan_bpu" 2
- (and (eq_attr "type" "branch,jmpreg,cr_logical,delayed_cr")
+ (and (eq_attr "type" "branch,jmpreg,cr_logical")
(eq_attr "cpu" "titan"))
"titan_issue,titan_bpu_sh")