From patchwork Wed May 24 09:41:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Mei X-Patchwork-Id: 1785655 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=oss.cipunited.com header.i=@oss.cipunited.com header.a=rsa-sha256 header.s=feishu2303200042 header.b=cjSxm5Zv; dkim-atps=neutral Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QR5p66bGlz20Pb for ; Wed, 24 May 2023 19:42:54 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E8D06381A894 for ; Wed, 24 May 2023 09:42:52 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from t03.bc.larksuite.com (t03.bc.larksuite.com [209.127.231.34]) by sourceware.org (Postfix) with UTF8SMTPS id 33BCD3858414 for ; Wed, 24 May 2023 09:41:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 33BCD3858414 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=oss.cipunited.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303200042; d=oss.cipunited.com; t=1684921276; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=rsb/1Lzga1LNtUMcBouqGWhEdqpkXaPqAi3bHFrnUbY=; b=cjSxm5Zv6LEbjcRgL0UC3G1hdRg6DKML5tEwz+sgsJ2tO8n4+NV+ugnrCOBds6YD9QLuV3 ca26xiXQcUOszSg/9UXscBDgVJLoNEC/HrPwuOzDPJB7ORiyq0Yn6m1r2UNW4B/2nPJbz/ SQ542DRMAjrmSryinkDT4lN+Au4Mjdr0cqJjLK+fruoUH290ga9w93wjLXDic/CPg47voG bSV36gvI23GKojgMeJc+Bb/x82vksRQAjFKRCVVcQ2NoT6zZcuEPyX9aNQ9REsIk5VVnxi Djw127XibVfERvs7akApYhliCYwsevDkMr3Z7YVoF3pAbsq7Ln1FVTqxD1JjQw== Subject: [PATCH v3 3/9] MIPS: Add instruction about global pointer register for mips16e2 X-Mailer: git-send-email 2.40.1 To: References: From: "Jie Mei" Date: Wed, 24 May 2023 17:41:15 +0800 Mime-Version: 1.0 In-Reply-To: X-Lms-Return-Path: Cc: "YunQiang Su" , "Maciej W . Rozycki" Message-Id: X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00, DKIM_ADSP_NXDOMAIN, DKIM_INVALID, DKIM_SIGNED, GIT_PATCH_0, HTML_MESSAGE, HTML_NONELEMENT_30_40, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, KAM_STOCKGEN, NO_DNS_FOR_FROM, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" The mips16e2 ASE uses eight general-purpose registers from mips32, with some special-purpose registers, these registers are GPRs: s0-1, v0-1, a0-3, and special registers: t8, gp, sp, ra. As mentioned above, the special register gp is used in mips16e2, which is the global pointer register, it is used by some of the instructions in the ASE, for instance, ADDIU, LB/LBU, etc. . This patch adds these instructions with corresponding tests. gcc/ChangeLog: * config/mips/mips.cc(mips_regno_mode_ok_for_base_p): Generate instructions that uses global pointer register. (mips16_unextended_reference_p): Same as above. (mips_pic_base_register): Same as above. (mips_init_relocs): Same as above. * config/mips/mips.h(MIPS16_GP_LOADS): Defined a new macro. (GLOBAL_POINTER_REGNUM): Moved to machine description `mips.md`. * config/mips/mips.md(GLOBAL_POINTER_REGNUM): Moved to here from above. (*lowsi_mips16_gp):New `define_insn *low_mips16`. gcc/testsuite/ChangeLog: * gcc.target/mips/mips16e2-gp.c: New tests for mips16e2. --- gcc/config/mips/mips.cc | 10 +- gcc/config/mips/mips.h | 6 +- gcc/config/mips/mips.md | 11 +++ gcc/testsuite/gcc.target/mips/mips16e2-gp.c | 101 ++++++++++++++++++++ 4 files changed, 121 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2-gp.c diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 585a3682c7b..be470bbb50d 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -2474,6 +2474,9 @@ mips_regno_mode_ok_for_base_p (int regno, machine_mode mode, if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM) return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8; + if (MIPS16_GP_LOADS && regno == GLOBAL_POINTER_REGNUM) + return (UNITS_PER_WORD > 4 ? GET_MODE_SIZE (mode) <= 4 : true); + return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno); } @@ -2689,7 +2692,8 @@ static bool mips16_unextended_reference_p (machine_mode mode, rtx base, unsigned HOST_WIDE_INT offset) { - if (mode != BLKmode && offset % GET_MODE_SIZE (mode) == 0) + if (mode != BLKmode && offset % GET_MODE_SIZE (mode) == 0 + && REGNO (base) != GLOBAL_POINTER_REGNUM) { if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx) return offset < 256U * GET_MODE_SIZE (mode); @@ -3249,7 +3253,7 @@ mips16_gp_pseudo_reg (void) rtx mips_pic_base_register (rtx temp) { - if (!TARGET_MIPS16) + if (MIPS16_GP_LOADS ||!TARGET_MIPS16) return pic_offset_table_rtx; if (currently_expanding_to_rtl) @@ -8756,7 +8760,7 @@ mips_init_relocs (void) } } - if (TARGET_MIPS16) + if (!MIPS16_GP_LOADS && TARGET_MIPS16) { /* The high part is provided by a pseudo copy of $gp. */ mips_split_p[SYMBOL_GP_RELATIVE] = true; diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index a94b253e898..3ec33fbba71 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1375,6 +1375,8 @@ struct mips_cpu_info { /* ISA includes the pop instruction. */ #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16) +#define MIPS16_GP_LOADS (ISA_HAS_MIPS16E2 && !TARGET_64BIT) + /* The CACHE instruction is available in non-MIPS16 code. */ #define TARGET_CACHE_BUILTIN (mips_isa >= MIPS_ISA_MIPS3) @@ -2067,10 +2069,6 @@ FP_ASM_SPEC "\ function address than to call an address kept in a register. */ #define NO_FUNCTION_CSE 1 -/* The ABI-defined global pointer. Sometimes we use a different - register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */ -#define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28) - /* We normally use $28 as the global pointer. However, when generating n32/64 PIC, it is better for leaf functions to use a call-clobbered register instead. They can then avoid saving and restoring $28 diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 48d5f419ce0..9de5013aad1 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -167,6 +167,7 @@ (GET_FCSR_REGNUM 2) (SET_FCSR_REGNUM 4) (PIC_FUNCTION_ADDR_REGNUM 25) + (GLOBAL_POINTER_REGNUM 28) (RETURN_ADDR_REGNUM 31) (CPRESTORE_SLOT_REGNUM 76) (GOT_VERSION_REGNUM 79) @@ -4678,6 +4679,16 @@ [(set_attr "alu_type" "add") (set_attr "mode" "")]) +(define_insn "*lowsi_mips16_gp" + [(set (match_operand:SI 0 "register_operand" "=d") + (lo_sum:SI (reg:SI GLOBAL_POINTER_REGNUM) + (match_operand 1 "immediate_operand" "")))] + "MIPS16_GP_LOADS" + "addiu\t%0,$28,%R1" + [(set_attr "alu_type" "add") + (set_attr "mode" "SI") + (set_attr "extended_mips16" "yes")]) + (define_insn "*low_mips16" [(set (match_operand:P 0 "register_operand" "=d") (lo_sum:P (match_operand:P 1 "register_operand" "0") diff --git a/gcc/testsuite/gcc.target/mips/mips16e2-gp.c b/gcc/testsuite/gcc.target/mips/mips16e2-gp.c new file mode 100644 index 00000000000..7955472bde3 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mips16e2-gp.c @@ -0,0 +1,101 @@ +/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 -mips16 -mmips16e2" } */ +/* { dg-skip-if "per-function expected output" { *-*-* } { "-flto" } { "" } } */ + +/* Generate GP-relative ADDIU. */ + +/* { dg-final { scan-assembler "test01:.*\taddiu\t\\\$2,\\\$28.*test01\n" } } */ +int arr[2]; + +int * +test01 (void) +{ + return (&arr[1]); +} + +/* Test LB[GP]. */ + +/* { dg-final { scan-assembler "test02:.*\tlb\t.*\\\$28.*test02\n" } } */ +signed char c02; + +signed char +test02 (void) +{ + return c02; +} + +/* Test LBU[GP]. */ + +/* { dg-final { scan-assembler "test03:.*\tlbu\t.*\\\$28.*test03\n" } } */ +unsigned char uc03; + +unsigned char +test03 (void) +{ + return uc03; +} + +/* Test LH[GP]. */ + +/* { dg-final { scan-assembler "test04:.*\tlh\t.*\\\$28.*test04\n" } } */ +short s04; + +short +test04 (void) +{ + return s04; +} + +/* Test LHU[GP]. */ + +/* { dg-final { scan-assembler "test05:.*\tlhu\t.*\\\$28.*test05\n" } } */ +unsigned short s05; + +unsigned short +test05 (void) +{ + return s05; +} + +/* Test LW[GP]. */ + +/* { dg-final { scan-assembler "test06:.*\tlw\t.*\\\$28.*test06\n" } } */ +int i06; + +int +test06 (void) +{ + return i06; +} + +/* Test SB[GP]. */ + +/* { dg-final { scan-assembler "test07:.*\tsb\t.*\\\$28.*test07\n" } } */ +char c07; + +void +test07 (char x) +{ + c07 = x; +} + +/* Test SH[GP]. */ + +/* { dg-final { scan-assembler "test08:.*\tsh\t.*\\\$28.*test08\n" } } */ +short s08; + +void +test08 (short x) +{ + s08 = x; +} + +/* Test SW[GP]. */ + +/* { dg-final { scan-assembler "test09:.*\tsw\t.*\\\$28.*test09\n" } } */ +int i09; + +void +test09 (int x) +{ + i09 = x; +}