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[committed,RISC-V] Trivial pattern cleanup

Message ID d313a4a7-d7d4-4248-bf35-9c1282882456@ventanamicro.com
State New
Headers show
Series [committed,RISC-V] Trivial pattern cleanup | expand

Commit Message

Jeff Law May 1, 2024, 6:49 p.m. UTC 
As I was reviewing and cleaning up some internal work, I noticed a 
particular idiom being used elsewhere in the RISC-V backend.

Specifically the use of explicit subregs when an adjustment to the 
match_operand would be sufficient.

Let's take this example from the and-not splitter:

>  (define_split
>    [(set (match_operand:X 0 "register_operand")
>         (and:X (not:X (lshiftrt:X (match_operand:X 1 "register_operand")
>                                   (subreg:QI (match_operand:X 2 "register_operand") 0)))
>                (const_int 1)))]


Note the explicit subreg.  We can instead use a match_operand with 
QImode.  This ever-so-slightly simplifies the machine description.

It also means that if we have a QImode object lying around (say we 
loaded it from memory in QImode), we can use it directly rather than 
first extending it to X, then truncing to QI.  So we end up with simpler 
RTL and in rare cases improve the code we generate.

When used in a define_split or define_insn_and_split we need to make 
suitable adjustments to the split RTL.

Bootstrapped a while back.  Just re-tested with a cross.

Pushing to the trunk & coordination branch.

jeff
commit 76ca6e1f8b1524b82a871ce29cf58c79e5e77e2b
Author: Jeff Law <jlaw@ventanamicro.com>
Date:   Wed May 1 12:43:37 2024 -0600

    [committed] [RISC-V] Trivial pattern cleanup
    
    As I was reviewing and cleaning up some internal work, I noticed a particular
    idiom being used elsewhere in the RISC-V backend.
    
    Specifically the use of explicit subregs when an adjustment to the
    match_operand would be sufficient.
    
    Let's take this example from the and-not splitter:
    
    >  (define_split
    >    [(set (match_operand:X 0 "register_operand")
    >         (and:X (not:X (lshiftrt:X (match_operand:X 1 "register_operand")
    >                                   (subreg:QI (match_operand:X 2 "register_operand") 0)))
    >                (const_int 1)))]
    
    Note the explicit subreg.  We can instead use a match_operand with QImode.
    This ever-so-slightly simplifies the machine description.
    
    It also means that if we have a QImode object lying around (say we loaded it
    from memory in QImode), we can use it directly rather than first extending it
    to X, then truncing to QI.  So we end up with simpler RTL and in rare cases
    improve the code we generate.
    
    When used in a define_split or define_insn_and_split we need to make suitable
    adjustments to the split RTL.
    
    Bootstrapped a while back.  Just re-tested with a cross.
    
    gcc/
            * config/riscv/bitmanip.md (splitter to use w-form division): Remove
            explicit subregs.
            (zero extended bitfield extraction): Similarly.
            * config/riscv/thead.md (*th_memidx_operand): Similarly.
diff mbox series

Patch

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index ccda25c01c1..ad3ad758959 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -50,11 +50,11 @@  (define_split
 	(sign_extend:DI (div:SI (plus:SI (ashift:SI (subreg:SI (match_operand:DI 1 "register_operand") 0)
 						    (match_operand:QI 2 "imm123_operand"))
 					 (subreg:SI (match_operand:DI 3 "register_operand") 0))
-				(subreg:SI (match_operand:DI 4 "register_operand") 0))))
+				(match_operand:SI 4 "register_operand"))))
    (clobber (match_operand:DI 5 "register_operand"))]
   "TARGET_64BIT && TARGET_ZBA"
    [(set (match_dup 5) (plus:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
-    (set (match_dup 0) (sign_extend:DI (div:SI (subreg:SI (match_dup 5) 0) (subreg:SI (match_dup 4) 0))))])
+    (set (match_dup 0) (sign_extend:DI (div:SI (subreg:SI (match_dup 5) 0) (match_dup 4))))])
 
 ; Zba does not provide W-forms of sh[123]add(.uw)?, which leads to an
 ; interesting irregularity: we can generate a signed 32-bit result
@@ -722,13 +722,14 @@  (define_insn "*bexti"
 (define_split
   [(set (match_operand:X 0 "register_operand")
 	(and:X (not:X (lshiftrt:X (match_operand:X 1 "register_operand")
-				  (subreg:QI (match_operand:X 2 "register_operand") 0)))
+				  (match_operand:QI 2 "register_operand")))
 	       (const_int 1)))]
   "TARGET_ZBS"
   [(set (match_dup 0) (zero_extract:X (match_dup 1)
 				      (const_int 1)
 				      (match_dup 2)))
-   (set (match_dup 0) (xor:X (match_dup 0) (const_int 1)))])
+   (set (match_dup 0) (xor:X (match_dup 0) (const_int 1)))]
+  "operands[2] = gen_lowpart (<MODE>mode, operands[2]);")
 
 ;; We can create a polarity-reversed mask (i.e. bit N -> { set = 0, clear = -1 })
 ;; using a bext(i) followed by an addi instruction.
diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
index 5c7d4beb1b6..a47fe6f28b8 100644
--- a/gcc/config/riscv/thead.md
+++ b/gcc/config/riscv/thead.md
@@ -466,12 +466,12 @@  (define_insn "*th_mempair_load_zero_extendsidi2"
 (define_insn_and_split "*th_memidx_operand"
   [(set (match_operand:DI 0 "register_operand" "=r")
      (ashift:DI
-       (zero_extend:DI (subreg:SI (match_operand:DI 1 "register_operand" "r") 0))
+       (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
        (match_operand 2 "const_int_operand" "n")))]
   "TARGET_64BIT && TARGET_XTHEADMEMIDX && lra_in_progress"
   "#"
   ""
-  [(set (match_dup 0) (zero_extend:DI (subreg:SI (match_dup 1) 0)))
+  [(set (match_dup 0) (zero_extend:DI (match_dup 1)))
    (set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))]
   ""
   [(set_attr "type" "bitmanip")])