| Message ID | cf2d74d5-23b1-4249-882e-175d7a6fcd96@linux.ibm.com |
|---|---|
| State | New |
| Headers | show |
| Series | rs6000: Add OPTION_MASK_POWER8 [PR101865] | expand |
Hi, on 2024/4/12 06:15, Peter Bergner wrote: > FYI: This patch is an update to Will Schmidt's patches to fix PR101865: > > https://gcc.gnu.org/pipermail/gcc-patches/2022-September/601825.html > https://gcc.gnu.org/pipermail/gcc-patches/2022-September/601823.html > > ...taking into consideration patch reviews received than. I also found > a few more locations that needed patching, as well as simplifying the > testsuite test cases by removing the need to scan for the predefined macros. > > > > The bug in PR101865 is the _ARCH_PWR8 predefined macro is conditional upon > TARGET_DIRECT_MOVE, which can be false for some -mcpu=power8 compiles if the > -mno-altivec or -mno-vsx options are used. The solution here is to create > a new OPTION_MASK_POWER8 mask that is true for -mcpu=power8, regardless of > Altivec or VSX enablement. > > Unfortunately, the only way to create an OPTION_MASK_* mask is to create > a new option, which we have done here, but marked it as WarnRemoved since > we do not want users using it. For stage1, we will look into how we can > create ISA mask flags for use in the compiler without the need for explicit > options. > > The passed bootstrap and regtest on powerpc64le-linux. Ok for trunk? Thanks for fixing this. I guess it should go well on powerpc64-linux too, but since it's very late stage4 now, could you also test this on BE machine? > > This is also broken on the release branches, so ok for backports after > some burn-in time on trunk? > > Peter > > > 2024-04-11 Will Schmidt <will_schmidt@linux.ibm.com> > Peter Bergner <bergner@linux.ibm.com> > > gcc/ > PR target/101865 > * config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use > TARGET_POWER8. > * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use > OPTION_MASK_POWER8. > * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add OPTION_MASK_POWER8. > (ISA_2_7_MASKS_SERVER): Likewise. > * config/rs6000/rs6000.cc (rs6000_option_override_internal): Update > comment. Use OPTION_MASK_POWER8 and TARGET_POWER8. > * config/rs6000/rs6000.h (TARGET_SYNC_HI_QI): Use TARGET_POWER8. > * config/rs6000/rs6000.md (define_attr "isa"): Add p8. > (define_attr "enabled"): Handle it. > (define_insn "prefetch"): Use TARGET_POWER8. > * config/rs6000/rs6000.opt (mdo-not-use-this-option): New. > > gcc/testsuite/ > PR target/101865 > * gcc.target/powerpc/predefined-p7-novsx.c: New test. > * gcc.target/powerpc/predefined-p8-noaltivec-novsx.c: New test. > * gcc.target/powerpc/predefined-p8-noaltivec.c: New test. > * gcc.target/powerpc/predefined-p8-novsx.c: New test. > * gcc.target/powerpc/predefined-p8-pragma-vsx.c: New test. > * gcc.target/powerpc/predefined-p9-novsx.c: New test. > > diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc > index e7d6204074c..320affd79e3 100644 > --- a/gcc/config/rs6000/rs6000-builtin.cc > +++ b/gcc/config/rs6000/rs6000-builtin.cc > @@ -165,7 +165,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode) > case ENB_P7_64: > return TARGET_POPCNTD && TARGET_POWERPC64; > case ENB_P8: > - return TARGET_DIRECT_MOVE; > + return TARGET_POWER8; > case ENB_P8V: > return TARGET_P8_VECTOR; > case ENB_P9: > diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc > index 647f20de7f2..bd493ab87c5 100644 > --- a/gcc/config/rs6000/rs6000-c.cc > +++ b/gcc/config/rs6000/rs6000-c.cc > @@ -429,7 +429,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) > rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6"); > if ((flags & OPTION_MASK_POPCNTD) != 0) > rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7"); > - if ((flags & OPTION_MASK_P8_VECTOR) != 0) > + if ((flags & OPTION_MASK_POWER8) != 0) > rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8"); > if ((flags & OPTION_MASK_MODULO) != 0) > rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9"); > diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def > index 45dd5a85901..6ee678e69c3 100644 > --- a/gcc/config/rs6000/rs6000-cpus.def > +++ b/gcc/config/rs6000/rs6000-cpus.def > @@ -47,6 +47,7 @@ > fusion here, instead set it in rs6000.cc if we are tuning for a power8 > system. */ > #define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \ > + | OPTION_MASK_POWER8 \ > | OPTION_MASK_P8_VECTOR \ > | OPTION_MASK_CRYPTO \ > | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ > @@ -130,6 +131,7 @@ > | OPTION_MASK_MODULO \ > | OPTION_MASK_MULHW \ > | OPTION_MASK_NO_UPDATE \ > + | OPTION_MASK_POWER8 \ > | OPTION_MASK_P8_FUSION \ > | OPTION_MASK_P8_VECTOR \ > | OPTION_MASK_P9_MINMAX \ > diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc > index c241371147c..117999613d8 100644 > --- a/gcc/config/rs6000/rs6000.cc > +++ b/gcc/config/rs6000/rs6000.cc > @@ -3807,11 +3807,10 @@ rs6000_option_override_internal (bool global_init_p) > "-mmultiple"); > } > > - /* If little-endian, default to -mstrict-align on older processors. > - Testing for direct_move matches power8 and later. */ > + /* If little-endian, default to -mstrict-align on older processors. */ > if (!BYTES_BIG_ENDIAN > && !(processor_target_table[tune_index].target_enable > - & OPTION_MASK_P8_VECTOR)) > + & OPTION_MASK_POWER8)) > rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN; > > /* Add some warnings for VSX. */ > @@ -3897,7 +3896,7 @@ rs6000_option_override_internal (bool global_init_p) > else > rs6000_isa_flags |= ISA_3_0_MASKS_SERVER; > } > - else if (TARGET_P8_VECTOR || TARGET_DIRECT_MOVE || TARGET_CRYPTO) > + else if (TARGET_P8_VECTOR || TARGET_POWER8 || TARGET_CRYPTO) > rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks); > else if (TARGET_VSX) > rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks); > diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h > index 77d045c9f6e..2cde2e329b0 100644 > --- a/gcc/config/rs6000/rs6000.h > +++ b/gcc/config/rs6000/rs6000.h > @@ -490,7 +490,7 @@ extern int rs6000_vector_align[]; > memory support. */ > #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \ > || TARGET_QUAD_MEMORY_ATOMIC \ > - || TARGET_DIRECT_MOVE) > + || TARGET_POWER8) > > #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC > > diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md > index bc8bc6ab060..ac5651d7420 100644 > --- a/gcc/config/rs6000/rs6000.md > +++ b/gcc/config/rs6000/rs6000.md > @@ -355,7 +355,7 @@ (define_attr "cpu" > (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) > > ;; The ISA we implement. > -(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10" > +(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10" > (const_string "any")) > > ;; Is this alternative enabled for the current CPU/ISA/etc.? > @@ -380,6 +380,10 @@ (define_attr "enabled" "" > (match_test "TARGET_VSX")) > (const_int 1) > > + (and (eq_attr "isa" "p8") > + (match_test "TARGET_POWER8")) > + (const_int 1) > + > (and (eq_attr "isa" "p8v") > (match_test "TARGET_P8_VECTOR")) > (const_int 1) > @@ -14305,7 +14309,7 @@ (define_insn "prefetch" > AIX does not support the dcbtstt and dcbtt extended mnemonics. > The AIX assembler does not support the three operand form of dcbt > and dcbtst on Power 7 (-mpwr7). */ > - int inst_select = INTVAL (operands[2]) || !TARGET_DIRECT_MOVE; > + int inst_select = INTVAL (operands[2]) || !TARGET_POWER8; > > if (REG_P (operands[0])) > { > diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt > index dfd5051b964..457c7d05e7e 100644 > --- a/gcc/config/rs6000/rs6000.opt > +++ b/gcc/config/rs6000/rs6000.opt > @@ -470,6 +470,10 @@ Save the TOC in the prologue for indirect calls rather than inline. > mvsx-timode > Target RejectNegative Undocumented Ignore > > +;; This option exists only to create its MASK. It is not intended for users. > +mdo-not-use-this-option > +Target RejectNegative Mask(POWER8) Var(rs6000_isa_flags) WarnRemoved > + I can understand the given name is to avoid users to use it, but it looks odd, personally I'm inclined to mpower8 (or even mpower8-internal) even if it's more likely to be used but it's a bit more meaningful (especially we already have mpower10), theoretically speaking it's undocumented users shouldn't use it at all. And I think we want explicit "Undocumented" here, and WarnRemoved seems not suitable here since it's for some option which worked before but then wasn't supported any longer, but this one is new, may be "Warn(Don't use %qs)" instead? [snip...] > diff --git a/gcc/testsuite/gcc.target/powerpc/predefined-p8-pragma-vsx.c b/gcc/testsuite/gcc.target/powerpc/predefined-p8-pragma-vsx.c > new file mode 100644 > index 00000000000..cb3cc16d968 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/predefined-p8-pragma-vsx.c > @@ -0,0 +1,101 @@ > +/* PR target/101865 */ > +/* { dg-do run } */ > +/* { dg-require-effective-target p8vector_hw } */ > +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ Nit: -O2 looks useless and can be dropped? The others look good to me, thanks! BR, Kewen > + > +/* Verify we correctly set our predefined macros in the face of #pragma usage. */ > + > +#include <stdio.h> > +#include <stdlib.h> > + > +volatile int power8_set; > +volatile int vsx_set; > +
On 4/11/24 10:31 PM, Kewen.Lin wrote: >> The passed bootstrap and regtest on powerpc64le-linux. Ok for trunk? > > Thanks for fixing this. I guess it should go well on powerpc64-linux too, > but since it's very late stage4 now, could you also test this on BE machine? Will do, after making the changes suggested below. >> +;; This option exists only to create its MASK. It is not intended for users. >> +mdo-not-use-this-option >> +Target RejectNegative Mask(POWER8) Var(rs6000_isa_flags) WarnRemoved >> + > > I can understand the given name is to avoid users to use it, but it looks odd, personally > I'm inclined to mpower8 (or even mpower8-internal) even if it's more likely to be used but > it's a bit more meaningful (especially we already have mpower10), theoretically speaking > it's undocumented users shouldn't use it at all. Sorry, I should have mentioned this, but I originally had it -mpower8, but given it was an option we don't want users to use, Segher mentioned offline to give it a name something like the above and not -mpower8. I kind of like -mpower8-internal now that you mention it, but I'd like Segher's input here whether he prefers -mdo-not-use-this-option or -mpower8-internal or something else??? > And I think we want explicit "Undocumented" here, and WarnRemoved seems not suitable here > since it's for some option which worked before but then wasn't supported any longer, but > this one is new, may be "Warn(Don't use %qs)" instead? Oops, yes, we want Undocumented here. Thanks for catching that! Good idea on the Warn versus WarnRemoved. >> +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ > > Nit: -O2 looks useless and can be dropped? Ok, I'll drop it. I'll make the changes above, modulo leaving the option name unchanged until we hear from Segher on that and report back on the LE and BE testing. Thanks! Peter
Hi! On Thu, Apr 11, 2024 at 11:23:02PM -0500, Peter Bergner wrote: > On 4/11/24 10:31 PM, Kewen.Lin wrote: > >> +;; This option exists only to create its MASK. It is not intended for users. > >> +mdo-not-use-this-option > >> +Target RejectNegative Mask(POWER8) Var(rs6000_isa_flags) WarnRemoved > >> + > > > > I can understand the given name is to avoid users to use it, but it looks odd, personally > > I'm inclined to mpower8 (or even mpower8-internal) even if it's more likely to be used but > > it's a bit more meaningful (especially we already have mpower10), theoretically speaking > > it's undocumented users shouldn't use it at all. > > Sorry, I should have mentioned this, but I originally had it -mpower8, but given > it was an option we don't want users to use, Segher mentioned offline to give it > a name something like the above and not -mpower8. I kind of like -mpower8-internal > now that you mention it, but I'd like Segher's input here whether he prefers > -mdo-not-use-this-option or -mpower8-internal or something else??? -mpower8-internal is fine. Anyone who thinks this would be a good thing to us, well, we cannot stop them from hurting themselves I guess. Esp. with a nice help text it is fine. Going forward we need something like this for most ISA levels (we currently often use the existence of some more-or-less random insn for this, but we need the same test to actually test for *that* insn, not a good thing at all). But we do not want the user to be able to use such options at all, so we really shouln't make command line options for it. So it should not use an option flag at all for this, but something else. Maybe something new even, we have had problems around this forever, that suggests we have insufficient abstractions around this :-) > I'll make the changes above, modulo leaving the option name unchanged until > we hear from Segher on that and report back on the LE and BE testing. -mpower8-internal should dissuade users from using it, certainly people who actually read the documentation as well. It is unfortunate we need to tell people to not use tools we provide ourselves, but this is temporary, right :-) (Right?!) Thanks guys, Segher
On 4/11/24 11:23 PM, Peter Bergner wrote: > I'll make the changes above, modulo leaving the option name unchanged until > we hear from Segher on that and report back on the LE and BE testing. I made all of the requested changes and went with -mpower8-internal since Segher was fine with that (offline) along with the helpful Warn message. Testing was clean on both LE and BE, so I pushed the changes. I'll let things bake on trunk for a bit before pushing the backports. Thanks! Peter
diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index e7d6204074c..320affd79e3 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -165,7 +165,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode) case ENB_P7_64: return TARGET_POPCNTD && TARGET_POWERPC64; case ENB_P8: - return TARGET_DIRECT_MOVE; + return TARGET_POWER8; case ENB_P8V: return TARGET_P8_VECTOR; case ENB_P9: diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index 647f20de7f2..bd493ab87c5 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -429,7 +429,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6"); if ((flags & OPTION_MASK_POPCNTD) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7"); - if ((flags & OPTION_MASK_P8_VECTOR) != 0) + if ((flags & OPTION_MASK_POWER8) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8"); if ((flags & OPTION_MASK_MODULO) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9"); diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 45dd5a85901..6ee678e69c3 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -47,6 +47,7 @@ fusion here, instead set it in rs6000.cc if we are tuning for a power8 system. */ #define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \ + | OPTION_MASK_POWER8 \ | OPTION_MASK_P8_VECTOR \ | OPTION_MASK_CRYPTO \ | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ @@ -130,6 +131,7 @@ | OPTION_MASK_MODULO \ | OPTION_MASK_MULHW \ | OPTION_MASK_NO_UPDATE \ + | OPTION_MASK_POWER8 \ | OPTION_MASK_P8_FUSION \ | OPTION_MASK_P8_VECTOR \ | OPTION_MASK_P9_MINMAX \ diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index c241371147c..117999613d8 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -3807,11 +3807,10 @@ rs6000_option_override_internal (bool global_init_p) "-mmultiple"); } - /* If little-endian, default to -mstrict-align on older processors. - Testing for direct_move matches power8 and later. */ + /* If little-endian, default to -mstrict-align on older processors. */ if (!BYTES_BIG_ENDIAN && !(processor_target_table[tune_index].target_enable - & OPTION_MASK_P8_VECTOR)) + & OPTION_MASK_POWER8)) rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN; /* Add some warnings for VSX. */ @@ -3897,7 +3896,7 @@ rs6000_option_override_internal (bool global_init_p) else rs6000_isa_flags |= ISA_3_0_MASKS_SERVER; } - else if (TARGET_P8_VECTOR || TARGET_DIRECT_MOVE || TARGET_CRYPTO) + else if (TARGET_P8_VECTOR || TARGET_POWER8 || TARGET_CRYPTO) rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks); else if (TARGET_VSX) rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks); diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 77d045c9f6e..2cde2e329b0 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -490,7 +490,7 @@ extern int rs6000_vector_align[]; memory support. */ #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \ || TARGET_QUAD_MEMORY_ATOMIC \ - || TARGET_DIRECT_MOVE) + || TARGET_POWER8) #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index bc8bc6ab060..ac5651d7420 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -355,7 +355,7 @@ (define_attr "cpu" (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) ;; The ISA we implement. -(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10" +(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10" (const_string "any")) ;; Is this alternative enabled for the current CPU/ISA/etc.? @@ -380,6 +380,10 @@ (define_attr "enabled" "" (match_test "TARGET_VSX")) (const_int 1) + (and (eq_attr "isa" "p8") + (match_test "TARGET_POWER8")) + (const_int 1) + (and (eq_attr "isa" "p8v") (match_test "TARGET_P8_VECTOR")) (const_int 1) @@ -14305,7 +14309,7 @@ (define_insn "prefetch" AIX does not support the dcbtstt and dcbtt extended mnemonics. The AIX assembler does not support the three operand form of dcbt and dcbtst on Power 7 (-mpwr7). */ - int inst_select = INTVAL (operands[2]) || !TARGET_DIRECT_MOVE; + int inst_select = INTVAL (operands[2]) || !TARGET_POWER8; if (REG_P (operands[0])) { diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index dfd5051b964..457c7d05e7e 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -470,6 +470,10 @@ Save the TOC in the prologue for indirect calls rather than inline. mvsx-timode Target RejectNegative Undocumented Ignore +;; This option exists only to create its MASK. It is not intended for users. +mdo-not-use-this-option +Target RejectNegative Mask(POWER8) Var(rs6000_isa_flags) WarnRemoved + mpower8-fusion Target Mask(P8_FUSION) Var(rs6000_isa_flags) Fuse certain integer operations together for better performance on power8. diff --git a/gcc/testsuite/gcc.target/powerpc/predefined-p7-novsx.c b/gcc/testsuite/gcc.target/powerpc/predefined-p7-novsx.c new file mode 100644 index 00000000000..bebe62d8f48 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/predefined-p7-novsx.c @@ -0,0 +1,22 @@ +/* PR target/101865 */ +/* { dg-do preprocess } */ +/* { dg-options "-mdejagnu-cpu=power7 -mno-vsx" } */ + +/* Verify we correctly set the correct set of predefined macros + for the given set of options. */ + +#ifndef _ARCH_PWR7 +#error "_ARCH_PWR7 should be defined for this test" +#endif + +#ifndef __ALTIVEC__ +#error "__ALTIVEC__ should be defined for this test" +#endif + +#ifdef _ARCH_PWR8 +#error "_ARCH_PWR8 should not be defined for this test" +#endif + +#ifdef __VSX__ +#error "__VSX__ should not be defined for this test" +#endif diff --git a/gcc/testsuite/gcc.target/powerpc/predefined-p8-noaltivec-novsx.c b/gcc/testsuite/gcc.target/powerpc/predefined-p8-noaltivec-novsx.c new file mode 100644 index 00000000000..9d118b44fe8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/predefined-p8-noaltivec-novsx.c @@ -0,0 +1,26 @@ +/* PR target/101865 */ +/* { dg-do preprocess } */ +/* { dg-options "-mdejagnu-cpu=power8 -mno-altivec -mno-vsx" } */ + +/* Verify _ARCH_PWR8 is defined for -mcpu=power8 and after disabling + both altivec and vsx. */ + +#ifndef _ARCH_PWR7 +#error "_ARCH_PWR7 should be defined for this test" +#endif + +#ifndef _ARCH_PWR8 +#error "_ARCH_PWR8 should be defined for this test" +#endif + +#ifdef _ARCH_PWR9 +#error "_ARCH_PWR9 should not be defined for this test" +#endif + +#ifdef __ALTIVEC__ +#error "__ALTIVEC__ should not be defined for this test" +#endif + +#ifdef __VSX__ +#error "__VSX__ should not be defined for this test" +#endif diff --git a/gcc/testsuite/gcc.target/powerpc/predefined-p8-noaltivec.c b/gcc/testsuite/gcc.target/powerpc/predefined-p8-noaltivec.c new file mode 100644 index 00000000000..5d2a7b852b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/predefined-p8-noaltivec.c @@ -0,0 +1,26 @@ +/* PR target/101865 */ +/* { dg-do preprocess } */ +/* { dg-options "-mdejagnu-cpu=power8 -mno-altivec -w" } */ + +/* Verify _ARCH_PWR8 is defined for -mcpu=power8 and after disabling altivec. + The -w option is used to silence the -mno-altivec disables -mvsx warning. */ + +#ifndef _ARCH_PWR7 +#error "_ARCH_PWR7 should be defined for this test" +#endif + +#ifndef _ARCH_PWR8 +#error "_ARCH_PWR8 should be defined for this test" +#endif + +#ifdef _ARCH_PWR9 +#error "_ARCH_PWR9 should not be defined for this test" +#endif + +#ifdef __ALTIVEC__ +#error "__ALTIVEC__ should not be defined for this test" +#endif + +#ifdef __VSX__ +#error "__VSX__ should not be defined for this test" +#endif diff --git a/gcc/testsuite/gcc.target/powerpc/predefined-p8-novsx.c b/gcc/testsuite/gcc.target/powerpc/predefined-p8-novsx.c new file mode 100644 index 00000000000..5eeadf421b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/predefined-p8-novsx.c @@ -0,0 +1,26 @@ +/* PR target/101865 */ +/* { dg-do preprocess } */ +/* { dg-options "-mdejagnu-cpu=power8 -mno-vsx" } */ + +/* Verify _ARCH_PWR8 is defined for -mcpu=power8 and after disabling vsx. + This also confirms __ALTIVEC__ remains set when VSX is disabled. */ + +#ifndef _ARCH_PWR7 +#error "_ARCH_PWR7 should be defined for this test" +#endif + +#ifndef _ARCH_PWR8 +#error "_ARCH_PWR8 should be defined for this test" +#endif + +#ifndef __ALTIVEC__ +#error "__ALTIVEC__ should be defined for this test" +#endif + +#ifdef _ARCH_PWR9 +#error "_ARCH_PWR9 should not be defined for this test" +#endif + +#ifdef __VSX__ +#error "__VSX__ should not be defined for this test" +#endif diff --git a/gcc/testsuite/gcc.target/powerpc/predefined-p8-pragma-vsx.c b/gcc/testsuite/gcc.target/powerpc/predefined-p8-pragma-vsx.c new file mode 100644 index 00000000000..cb3cc16d968 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/predefined-p8-pragma-vsx.c @@ -0,0 +1,101 @@ +/* PR target/101865 */ +/* { dg-do run } */ +/* { dg-require-effective-target p8vector_hw } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ + +/* Verify we correctly set our predefined macros in the face of #pragma usage. */ + +#include <stdio.h> +#include <stdlib.h> + +volatile int power8_set; +volatile int vsx_set; + +void +test_default (void) +{ +#ifdef _ARCH_PWR8 + power8_set=1; +#else + power8_set=0; +#endif +#ifdef __VSX__ + vsx_set=1; +#else + vsx_set=0; +#endif +} + +#pragma GCC target "no-vsx" +void +test_no_vsx (void) +{ +#ifdef _ARCH_PWR8 + power8_set=1; +#else + power8_set=0; +#endif +#ifdef __VSX__ + vsx_set=1; +#else + vsx_set=0; +#endif +} + +#pragma GCC reset_options +void +test_reset_options (void) +{ +#ifdef _ARCH_PWR8 + power8_set=1; +#else + power8_set=0; +#endif +#ifdef __VSX__ + vsx_set=1; +#else + vsx_set=0; +#endif +} + +int +main (void) +{ + test_default (); + if (!power8_set) + { + printf ("_ARCH_PWR8 is not set.\n"); + abort (); + } + if (!vsx_set) + { + printf ("__VSX__ is not set.\n"); + abort (); + } + + test_no_vsx (); + if (!power8_set) + { + printf ("_ARCH_PWR8 is not set.\n"); + abort (); + } + if (vsx_set) + { + printf ("__VSX__ is unexpectedly set.\n"); + abort (); + } + + test_reset_options (); + if (!power8_set) + { + printf ("_ARCH_PWR8 is not set.\n"); + abort (); + } + if (!vsx_set) + { + printf ("__VSX__ is not set.\n"); + abort (); + } + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/predefined-p9-novsx.c b/gcc/testsuite/gcc.target/powerpc/predefined-p9-novsx.c new file mode 100644 index 00000000000..d8f12275fd0 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/predefined-p9-novsx.c @@ -0,0 +1,26 @@ +/* PR target/101865 */ +/* { dg-do preprocess } */ +/* { dg-options "-mdejagnu-cpu=power9 -mno-vsx" } */ + +/* Verify _ARCH_PWR8 is defined for -mcpu=power9 and after disabling vsx. + This also confirms __ALTIVEC__ remains set when VSX is disabled. */ + +#ifndef _ARCH_PWR7 +#error "_ARCH_PWR7 should be defined for this test" +#endif + +#ifndef _ARCH_PWR8 +#error "_ARCH_PWR8 should be defined for this test" +#endif + +#ifndef _ARCH_PWR9 +#error "_ARCH_PWR9 should be defined for this test" +#endif + +#ifndef __ALTIVEC__ +#error "__ALTIVEC__ should be defined for this test" +#endif + +#ifdef __VSX__ +#error "__VSX__ should not be defined for this test" +#endif