diff mbox series

loongarch: fix mulsidi3_64bit instruction

Message ID cb51fe6d45969bcf55bfb9053cf78c25849cbc69.camel@xry111.site
State New
Headers show
Series loongarch: fix mulsidi3_64bit instruction | expand

Commit Message

Xi Ruoyao July 8, 2022, 1:18 p.m. UTC 
I think this should be obvious.  Ok for trunk and gcc-12 branch?

(Note: this bug really amazed me.  It's just a simple typo and all of us
failed to spot it reviewing the LoongArch port.  Incredibly, it can be
reproduced with such a simple test case (in the patch) but did not blow
the entire system up.  I didn't see anything abnormal until it blown up
two UBSan test cases when I tried to port UBSan for LoongArch.)

-- >8 --

(mult (sign_extend:DI rj:SI) (sign_extend:DI rk:SI)) should be
"mulw.d.w", not "mul.d".

gcc/ChangeLog:

	* config/loongarch/loongarch.md (mulsidi3_64bit): Use mulw.d.w
	instead of mul.d.

gcc/testsuite/ChangeLog:

	* gcc.target/loongarch/mul-1.c: New test.
	* gcc.target/loongarch/mul-2.c: New test.
---
 gcc/config/loongarch/loongarch.md          |  2 +-
 gcc/testsuite/gcc.target/loongarch/mul-1.c | 20 ++++++++++++++++++++
 gcc/testsuite/gcc.target/loongarch/mul-2.c | 10 ++++++++++
 3 files changed, 31 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/mul-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/mul-2.c

Comments

Xi Ruoyao July 8, 2022, 1:31 p.m. UTC | #1 
v2: Move one portable test to gcc.c-torture so it will be tested with
all optimization levels.  And it might be helpful if the engineer of the
next GCC port makes a similar typo :).

-- >8 --

(mult (sign_extend:DI rj:SI) (sign_extend:DI rk:SI)) should be
"mulw.d.w", not "mul.d".

gcc/ChangeLog:

	* config/loongarch/loongarch.md (mulsidi3_64bit): Use mulw.d.w
	instead of mul.d.

gcc/testsuite/ChangeLog:

	* gcc.target/loongarch/mulw_d_w.c: New test.
	* gcc.c-torture/execute/mul-sext.c: New test.
---
 gcc/config/loongarch/loongarch.md             |  2 +-
 .../gcc.c-torture/execute/mul-sext.c          | 20 +++++++++++++++++++
 gcc/testsuite/gcc.target/loongarch/mulw_d_w.c | 10 ++++++++++
 3 files changed, 31 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.c-torture/execute/mul-sext.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/mulw_d_w.c

diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index d3c809e25f3..8f8412fba84 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -621,7 +621,7 @@ (define_insn "mulsidi3_64bit"
 	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
 		 (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
   "TARGET_64BIT"
-  "mul.d\t%0,%1,%2"
+  "mulw.d.w\t%0,%1,%2"
   [(set_attr "type" "imul")
    (set_attr "mode" "DI")])
 
diff --git a/gcc/testsuite/gcc.c-torture/execute/mul-sext.c b/gcc/testsuite/gcc.c-torture/execute/mul-sext.c
new file mode 100644
index 00000000000..8b6800804fb
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/mul-sext.c
@@ -0,0 +1,20 @@
+/* { dg-do run } */
+
+typedef __INT64_TYPE__ int64_t;
+typedef __INT32_TYPE__ int32_t;
+
+/* f() was misoptimized to a single "mul.d" instruction on LA64.  */
+__attribute__((noipa, noinline)) int64_t
+f(int64_t a, int64_t b)
+{
+  return (int64_t)(int32_t)a * (int64_t)(int32_t)b;
+}
+
+int
+main()
+{
+  int64_t a = 0x1145140000000001;
+  int64_t b = 0x1919810000000001;
+  if (f(a, b) != 1)
+    __builtin_abort();
+}
diff --git a/gcc/testsuite/gcc.target/loongarch/mulw_d_w.c b/gcc/testsuite/gcc.target/loongarch/mulw_d_w.c
new file mode 100644
index 00000000000..a9a713210df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/mulw_d_w.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mabi=lp64d" } */
+/* { dg-final { scan-assembler "mulw.d.w\t\\\$r4,\\\$r5,\\\$r4" } } */
+
+/* This should be optimized to mulw.d.w for LA64.  */
+__attribute__((noipa, noinline)) long
+f(long a, long b)
+{
+  return (long)(int)a * (long)(int)b;
+}
diff mbox series

Patch

diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index d3c809e25f3..8f8412fba84 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -621,7 +621,7 @@  (define_insn "mulsidi3_64bit"
 	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
 		 (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
   "TARGET_64BIT"
-  "mul.d\t%0,%1,%2"
+  "mulw.d.w\t%0,%1,%2"
   [(set_attr "type" "imul")
    (set_attr "mode" "DI")])
 
diff --git a/gcc/testsuite/gcc.target/loongarch/mul-1.c b/gcc/testsuite/gcc.target/loongarch/mul-1.c
new file mode 100644
index 00000000000..8b6800804fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/mul-1.c
@@ -0,0 +1,20 @@ 
+/* { dg-do run } */
+
+typedef __INT64_TYPE__ int64_t;
+typedef __INT32_TYPE__ int32_t;
+
+/* f() was misoptimized to a single "mul.d" instruction on LA64.  */
+__attribute__((noipa, noinline)) int64_t
+f(int64_t a, int64_t b)
+{
+  return (int64_t)(int32_t)a * (int64_t)(int32_t)b;
+}
+
+int
+main()
+{
+  int64_t a = 0x1145140000000001;
+  int64_t b = 0x1919810000000001;
+  if (f(a, b) != 1)
+    __builtin_abort();
+}
diff --git a/gcc/testsuite/gcc.target/loongarch/mul-2.c b/gcc/testsuite/gcc.target/loongarch/mul-2.c
new file mode 100644
index 00000000000..a9a713210df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/mul-2.c
@@ -0,0 +1,10 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O2 -mabi=lp64d" } */
+/* { dg-final { scan-assembler "mulw.d.w\t\\\$r4,\\\$r5,\\\$r4" } } */
+
+/* This should be optimized to mulw.d.w for LA64.  */
+__attribute__((noipa, noinline)) long
+f(long a, long b)
+{
+  return (long)(int)a * (long)(int)b;
+}