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[committed] amdgcn: Allow vector reductions on constants

Message ID c430e5e1-24ea-6fe0-aec0-9328983d68c6@codesourcery.com
State New
Headers show
Series [committed] amdgcn: Allow vector reductions on constants | expand

Commit Message

Andrew Stubbs Feb. 14, 2022, 2:13 p.m. UTC 
I've committed this fix for an ICE compiling sollve_vv testcase 
test_target_teams_distribute_defaultmap.c.

Somehow the optimizers result in a vector reduction on a vector of 
duplicated constants. This was a case the backend didn't handle, so we 
ended up with an unrecognised instruction ICE.

It might be better if constant reductions were evaluated at compile 
time, but this patch prevents the ICE right now.

Andrew

P.S. I'll backport this to OG11 shortly.
amdgcn: Allow vector reductions on constants

Obviously it would be better if these reductions could be evaluated at compile
time, but this will avoid an ICE.

gcc/ChangeLog:

	* config/gcn/gcn.cc (gcn_expand_reduc_scalar): Use force_reg.

Comments

Andrew Stubbs Feb. 14, 2022, 3:57 p.m. UTC | #1 
On 14/02/2022 14:13, Andrew Stubbs wrote:
> I've committed this fix for an ICE compiling sollve_vv testcase 
> test_target_teams_distribute_defaultmap.c.
> 
> Somehow the optimizers result in a vector reduction on a vector of 
> duplicated constants. This was a case the backend didn't handle, so we 
> ended up with an unrecognised instruction ICE.
> 
> It might be better if constant reductions were evaluated at compile 
> time, but this patch prevents the ICE right now.
> 
> Andrew
> 
> P.S. I'll backport this to OG11 shortly.

Backport to devel/omp/gcc-11 branch done.

Andrew
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Patch

diff --git a/gcc/config/gcn/gcn.cc b/gcc/config/gcn/gcn.cc
index 74819c6e4d7..402f0256411 100644
--- a/gcc/config/gcn/gcn.cc
+++ b/gcc/config/gcn/gcn.cc
@@ -4460,7 +4460,7 @@  gcn_expand_reduc_scalar (machine_mode mode, rtx src, int unspec)
      pair of lanes, then on every pair of results from the previous
      iteration (thereby effectively reducing every 4 lanes) and so on until
      all lanes are reduced.  */
-  rtx in, out = src;
+  rtx in, out = force_reg (mode, src);
   for (int i = 0, shift = 1; i < 6; i++, shift <<= 1)
     {
       rtx shift_val = gen_rtx_CONST_INT (VOIDmode, shift);